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US 2003/0200474 A1Published application
Clock control apparatus and method for a memory controller
AssigneeFujitsu Limited
InventorJiang Li
Life of this patent
Estimating the term…
Abstract
A clock control apparatus for a memory controller comprises an interface unit which processes a block access to a plurality of banks of an SDRAM as a single continuous macro access in order to perform arbitration of the macro access, the block access externally supplied to the memory controller. A power-saving control unit controls both a clock signal of an internal circuit of the memory controller and a clock enable signal of the SDRAM in response to a control signal supplied from the interface unit.
Claims8
A clock control apparatus for a memory controller, comprising:
- an interface unit which processes a block access to a plurality of banks of an SDRAM as a single continuous macro access in order to perform arbitration of the macro access, the block access externally supplied to the memory controller;
- and
- a power-saving control unit which controls both a clock signal of an internal circuit of the memory controller and a clock enable signal of the SDRAM in response to a control signal supplied from the interface unit.
A clock control method of a memory controller, comprising the steps of:
- processing a block access to a plurality of banks of an SDRAM as a single continuous macro access in order to perform arbitration of the macro access, the block access externally supplied to the memory controller;
- and
- controlling both a clock signal of an internal circuit of the memory controller and a clock enable signal of the SDRAM in response to a control signal supplied during the arbitration of the macro access.
Dependencies are inferred from the claim text.