Master-slave latch circuit for multithreaded processing
AssigneeInternational Business Machines Corporation
InventorsAnthony Gus Aipperspach, Merwin Herscher Alferness, Gregory John Uhlmann
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Abstract
A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in multiple modes, including a scan mode for testing purposes.
Claims18
A master-slave latch circuit for use in a multithreaded processor, comprising:
- a plurality of master elements, each master element storing a state corresponding to a respective thread supported by said multithreaded processor;
- selection logic coupled to the outputs of said master elements, said selection logic selecting a single one of said outputs of said master elements in response to a thread designation input;
- and
- a common slave element coupled to said selection logic, said common slave element receiving as input and storing the selected single one of said outputs of said master elements.
A multithreaded processor supporting concurrent processing of a plurality of threads, comprising:
- at least one register for storing data for each of said plurality of threads, said register comprising a plurality of master-slave latch circuits, each master-slave latch circuit comprising:
- (a) a plurality of master elements, each master element storing a state corresponding to a respective thread supported by said multithreaded processor;
- (b) selection logic coupled to the outputs of said master elements, said selection logic selecting a single one of said outputs of said master elements in response to a thread designation input;
- and
- (c) a common slave element coupled to said selection logic, said common slave element receiving as input and storing the selected single one of said outputs of said master elements.
A computer system for supporting hardware multithreading, comprising:
- a memory for storing instructions and data for a plurality of threads;
- at least one multithreaded processor communicating with said memory and supporting concurrent processing of a plurality of threads, said processor having at least one register for storing data for each of said plurality of threads, said register comprising a plurality of master-slave latch circuits, each master-slave latch circuit comprising:
- (a) a plurality of master elements, each master element storing a state corresponding to a respective thread supported by said multithreaded processor;
- (b) selection logic coupled to the outputs of said master elements, said selection logic selecting a single one of said outputs of said master elements in response to a thread designation input;
- and
- (c) a common slave element coupled to said selection logic, said common slave element receiving as input and storing the selected single one of said outputs of said master elements.
A multi-stage latch circuit for use in a multithreaded processor, comprising:
- a first stage having a plurality of first stage memory elements, each first stage memory element corresponding to a respective thread supported by said multithreaded processor, each said first stage memory element storing a state corresponding to a respective input at times determined by a first phase of a clock signal;
- selection logic coupled to the outputs of said first stage memory elements, said selection logic selecting a single one of said outputs of said first stage memory elements in response to a thread designation input;
- and
- a common second stage memory element coupled to said selection logic and receiving as input the selected single one of said outputs of said first stage memory elements, said common second stage memory element storing a state corresponding to said selected single one of said outputs of said first stage memory elements at times determined by a second phase of said clock signal, said second phase being different from said first phase.
Dependencies are inferred from the claim text.