Parallel processor
AssigneeSemiconductor Technology Academic Research Center
InventorsTetsuo Hironaka, Mattausch Hans Juergen, Takeshi Hiramatsu
Life of this patent
Estimating the term…
Abstract
A parallel processor has a plurality of operation units that execute operation instructions, and a multi-bank register file in which a plurality of banks each having a plurality of registers are formed. Each of simultaneously input machine instructions is split into a plurality of nano-instructions each of which includes at least one of an access instruction and operation instruction. The output clock cycles of operation instructions with respect to the operation units are arbitrated. Furthermore, the output clock cycles of access instructions to the multi-bank register file are arbitrated so as to prevent access instructions from contending in an identical bank in the multi-bank register file.
Claims8
A parallel processor which simultaneously executes a plurality of instructions in one clock cycle, comprising:
- an instruction change unit which splits each of a plurality of simultaneously input machine instructions into a plurality of nano-instructions each of which includes at least one of an access instruction and an operation instruction;
- a plurality of operation units which execute operation instructions split by the instruction change unit;
- a multi-bank register file in which a plurality of banks each having a plurality of registers are formed, and which is accessed by an access instruction which is split by the instruction change unit and designates a bank and register;
- a plurality of operation arbitrators, which are interposed between the instruction change unit and the operation units, and arbitrate output clock cycles of operation instructions output from the instruction change unit with respect to the operation units;
- an access arbitrator which is interposed between the instruction change unit and the multi-bank register file, and arbitrates output clock cycles of respective access instructions with respect to the multi-bank register file so as to prevent the access instructions simultaneously output from the instruction change unit from contending in an identical bank;
- and
- an execution result bus which feeds back access results to the multi-bank register file, and operation results in the operation units to the operation and access arbitrators.
A parallel processor comprising:
- a multi-bank register file in which a plurality of banks, each of which incorporates a plurality of registers, are formed;
- and
- execution means for simultaneously executing a plurality of access instructions that designate bank addresses and a register address in each bank with respect to the multi-bank register file in one clock cycle,
- the multi-bank register file including:
- a plurality of banks;
- a bank row select circuit which outputs a bank row select signal to respective banks that belong to a row designated by the bank address;
- a bank column select circuit which outputs a bank column select signal to respective banks that belong to a column designated by the bank address;
- and
- a bank read/write circuit which executes access to a register designated by the register address in the bank designated by the bank row and column select signals.
A parallel processor comprising:
- a multi-bank register file in which a plurality of banks, each of which incorporates a plurality of registers, are formed;
- and
- execution means for simultaneously executing a plurality of access instructions that designate bank addresses and a register address in each bank with respect to the multi-bank register file in one clock cycle,
- the multi-bank register file including:
- a plurality of banks;
- a bank row select circuit which outputs a bank row select signal to respective banks that belong to a row designated by the bank address;
- a bank column select circuit which outputs a bank column select signal to respective banks that belong to a column designated by the bank address;
- and
- a bank read/write circuit which executes access to a register designated by the register address in the bank designated by the row and column bank select signals,
- each bank including:
- a plurality of registers;
- a register row select circuit which outputs a register row select signal to respective registers that belong to a row designated by the register address designated by the bank read/write instruction circuit;
- a register column select circuit which outputs a register column select signal to respective registers that belong to a column designated by the register address designated by the bank read/write instruction circuit;
- and
- a register read/write circuit which executes access, that is instructed by the bank read/write instruction circuit, to the register designated by the row and column register select signals.
Dependencies are inferred from the claim text.