Reducing data hazards in pipelined processors to provide high processor utilization

A method of operating a pipelined computer processor, said method comprising:

• processing a first subset of instructions operating on a first piece of data in a first pass;
• processing said first subset of instructions operating on a second piece of data in a second pass;
• processing a second subset of instructions operating on said first piece of data in said second pass;
• and
• processing said second subset of instructions operating on said second piece of data in a third pass, wherein:
• said first and second subsets are part of a computer program comprising a set of instructions, and
• said first, second, and third passes each comprise a number of clock cycles, said clock cycles for said first, second, and third passes occurring sequentially from a first cycle of said first pass to a last cycle of said third pass.

A method of operating a pipelined computer processor, said method comprising:

• processing a first subset of instructions operating on a first piece of data in a first pass;
• processing said first subset of instructions operating on a second piece of data in a second pass;
• processing a second subset of instructions operating on said first piece of data in said second pass;
• processing said first subset of instructions operating on a third piece of data in a third pass;
• processing said second subset of instructions operating on said second piece of data in said third pass;
• and
• processing a third subset of instructions operating on said first piece of data in said third pass;
• wherein:
• said first, second, and third subsets are part of a computer program comprising a set of instructions, and
• said first, second, and third passes each comprise a number of clock cycles, said clock cycles for said first, second, and third passes occurring sequentially from a first cycle of said first pass to a last cycle of said third pass.

A method of operating a pipelined computer processor, said method comprising:

• dividing a set of instructions into a plurality of subsets of instructions;
• allocating a group of physical registers, each physical register identified by a register number;
• assigning each physical register of said group a same temporary register value;
• and
• calculating one of said physical register numbers that corresponds both to said temporary register value and to a piece of data processed by said set of instructions.

A method of operating a pipelined computer processor, said method comprising:

• dividing a set of instructions into a plurality of subsets of instructions;
• allocating a group of physical registers;
• assigning each physical register of said group a same temporary register value;
• and
• calculating a physical register number that corresponds to said temporary register value and to a piece of data processed by said set of instructions as follows:
• (Register*NumberofPasses)+(CurrentPass−PassUsed) % NumberOfPasses,
• wherein said Register is said temporary register value encoded in an instruction, said NumberOfPasses is a number of subsets, said PassUsed is a pass number of a particular subset of instructions encoded in an instruction;
• said CurrentPass is measured from when a first subset of instructions for a given piece of data is processed, and said % represents an integer remainder from a division operation.

A method of operating a pipelined computer processor, said method comprising:

• dividing a set of instructions into a plurality of subsets of instructions;
• assigning a base address for a piece of data;
• assigning an offset value to an output that results from processing said set of instructions on said piece of data;
• and
• storing said output at an address determined by combining said base address and said offset value corresponding to said output.

A computer processor operative to process a set of instructions, said processor comprising an instruction pipeline that:

• processes a first subset of instructions on a first piece of data in a first pass,
• processes said first subset on a second piece of data and a second subset of instructions on said first piece of data in a second pass, and
• processes said second subset on said second piece of data in a third pass, wherein:
• said first and second subsets are part of a computer program comprising a set of instructions, and
• said first, second, and third passes each comprise a number of clock cycles, said clock cycles for is said first, second, and third passes occurring sequentially from a first cycle of said first pass to a last cycle of said third pass.

A computer processor operative to process a set of instructions, said processor comprising:

• an instruction pipeline that:
• processes a first subset of instructions on a first piece of data in a first pass,
• processes said first subset on a second piece of data and a second subset of instructions on said first piece of data in a second pass, and
• processes said second subset on said second piece of data in a third pass;
• and
• a validity pipeline coupled to said instruction pipeline that:
• assigns a bit indicating validity in a first stage of said validity pipeline upon processing of said first subset, wherein said bit is set to a first state when said first piece of data is valid and is otherwise set to a second state when said first piece of data is not valid, and
• propagates said validity bit to a next stage of said validity pipeline upon processing of said second subset operating on said first piece of data, wherein:
• said first and second subsets are part of a computer program comprising a set of instructions, and
• said first, second, and third passes each comprise a number of clock cycles, said clock cycles for said first, second, and third passes occurring sequentially from a first cycle of said first pass to a last cycle of said third pass.

Apparatus for operating a pipelined computer processor, said apparatus comprising:

• means for identifying program instructions dependent upon results of prior program instructions in a set of instructions;
• means for dividing said set of instructions into a plurality of subsets of instructions, each subset comprising a number of instructions from said set of instructions, each instruction of said set belonging to only one subset;
• and
• means for processing at least two of said subsets concurrently, each of said two subsets operating on a different piece of input data.

Apparatus for operating a pipelined computer processor, said apparatus comprising:

• means for processing a first subset of instructions operating on a first piece of data in a first pass;
• means for processing said first subset of instructions operating on a second piece of data in a second pass;
• means for processing a second subset of instructions operating on said first piece of data in said second pass;
• and
• means for processing said second subset of instructions operating on said second piece of data in a third pass, wherein:
• said first and second subsets are part of a computer program comprising a set of instructions, and
• said first, second, and third passes each comprise a number of clock cycles, said clock cycles for said first, second, and third passes occurring sequentially from a first cycle of said first pass to a last cycle of said third pass.

Apparatus for operating a pipelined computer processor, said apparatus comprising:

• means for dividing a set of instructions into a plurality of subsets of instructions;
• means for allocating a group of physical registers, each physical register identified by a register number;
• means for assigning each physical register of said group a same temporary register value;
• and
• means for calculating one of said physical register numbers that corresponds to said temporary register value and to a piece of data processed by said set of instructions.