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US 2003/0200404 A1Published application
N-way set-associative external cache with standard DDR memory devices
AssigneeSun Microsystems, Inc.
InventorsThomas M. Wicki, Koen R.C. Bennebroek
Life of this patent
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Abstract
A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags.
Claims51
A method for storing information in a cache, comprising:
- storing a first tag data in a first storage location in a memory device, wherein the first tag data is associated with a first location in a memory level device;
- storing a second tag data in a second storage location in the memory device, the second storage location being contiguous to the first storage location, the second tag data being associated with a second location in the memory level device;
- storing the contents of the first memory level device location in a third storage location in the memory device, the third storage location being contiguous to the second memory location;
- and
- storing the contents of the second memory level device location in a fourth storage location in the memory device, the fourth storage location being contiguous to the third storage location.
2 more elements
A method for storing information in a cache, comprising:
- storing the contents of a first tag row in one of a plurality of n contiguous storage locations in a memory device, wherein the contents of the first tag row is associated with a first of n locations in a memory level device;
- storing the contents of a second tag row in another one of the plurality of n contiguous storage locations in the memory device, wherein the contents of the second tag row is associated with a second one of the n locations in the memory level device;
- storing the contents of the first memory level device location in a contiguous subset of a plurality of m contiguous storage locations in the memory device, wherein the plurality of m contiguous storage locations follow the n contiguous storage locations in a contiguous relationship within the memory device, wherein the contiguous subset comprises q of the m storage locations, where m/n=q;
- and
- storing the contents of the second memory level device location in another contiguous subset of the plurality of m contiguous storage locations in the memory device, wherein the other contiguous subset comprises q of the m storage locations, where m/n q.
2 more elements
A cache system, comprising:
- a memory device;
- means for storing a first tag data in a first storage location in the memory device, wherein the first tag data is associated with a first location in a memory level device;
- means for storing a second tag data in a second storage location in the memory device, the second storage location being contiguous to the first storage location, the second tag data being associated with a second location in the memory level device;
- means for storing the contents of the first memory level device location in a third storage location in the memory device, the third storage location being contiguous to the second memory location;
- and
- means for storing the contents of the second main memory location in a fourth storage location in the memory level device, the fourth storage location being contiguous to the third storage location.
3 more elements
A cache system, comprising:
- a memory device;
- means for storing the contents of a first tag row in one of a plurality of n contiguous storage locations in the memory device, wherein the contents of the first tag row is associated with a first of n locations in a memory level device;
- means for storing the contents of a second tag row in another one of the plurality of n contiguous storage locations in the memory device, wherein the contents of the second tag row is associated with a second one of the n locations in the main memory;
- means for storing the contents of the first memory level device location in a subset of a plurality of m contiguous storage locations in the memory device, the means for storing further comprising a means for organizing the m contiguous storage locations to follow the n contiguous storage locations in a contiguous relationship within the memory device, wherein the subset comprises q of the m storage locations, where m/n=q;
- and
- means for storing the contents of the second memory level device location in another subset of the plurality of m contiguous storage locations in the memory device wherein the other subset comprises q of the m storage locations, where m/n=q.
3 more elements
The cache system recited in claim 35, wherein:
- the memory device further comprises means for incrementing a base address by an integer multiple of 4 for each cache row, besides the initial row, transmitted during a burst transmission.
A cache controller, comprising:
- logic that stores a first tag data in a first storage location in a memory device, wherein the first tag data is associated with a first location in a memory level device;
- logic that stores a second tag data in a second storage location in the memory device, the second storage location being contiguous to the first storage location, the second tag data being associated with a second location in the memory level device;
- logic that stores the contents of the first main memory location in a third storage location in the memory device, the third storage location being contiguous to the second memory location;
- and
- logic that stores the contents of the second main memory location in a fourth storage location in the memory device, the fourth storage location being contiguous to the third storage location.
2 more elements
A cache controller, comprising:
- logic that stores the contents of a first tag row in one of a plurality of n contiguous storage locations in a memory device, wherein the contents of the first tag row is associated with a first of n locations in a memory level device;
- logic that stores the contents of a second tag row in another one of the plurality of n contiguous storage locations in the memory device, wherein the contents of the second tag row is associated with a second one of the n locations in the memory level device;
- logic that stores the contents of the first memory level device location in a contiguous subset of a plurality of m contiguous storage locations in the memory device, wherein the plurality of m contiguous storage locations follow the n contiguous storage locations in a contiguous relationship within the memory device, wherein the contiguous subset comprises q of the m storage locations, where m/n=q;
- and
- logic that stores the contents of the second memory level device location in another contiguous subset of the plurality of m contiguous storage locations in the memory device, wherein the other contiguous subset comprises q of the m storage locations, where m/n=q.
2 more elements
Dependencies are inferred from the claim text.