Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent

Abstract

A memory controller provides memory line caching and memory transaction coherency by using at least one memory controller agent. A memory controller in accordance with the present invention includes at least one memory controller agent, an incoming memory transaction dispatch unit, and an outgoing memory transaction completion unit. Each memory controller agent has a memory line memory controller and a memory line coherency controller, along with a cache memory capable of caching the contents of a memory line along with coherency information for the memory line. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to one or more agents. For each incoming transaction, one of the agents will accept the transaction. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests. Since coherency information and memory line data associated with each memory line is cached by each agent, repeated requests to the same memory line are serviced more quickly. When two or more agents are queued up to fulfill multiple memory read transactions to the same memory line, the agents cooperate by transferring the cached coherency information and memory line data associated with each memory line from agent to agent, thereby minimizing the need to access main memory. The agents complete memory transactions back to the cacheable entities via the outgoing memory transaction completion unit.

Dependencies are inferred from the claim text.