Latched address multi-chunk write to EEPROM
OwnerDouglas J. Lee, Mehrdad Mofidi +2inventors
InventorsDouglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
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Abstract
An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.
Claims18
A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays, comprising:
- a plurality of address latches,
- a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays,
- means for storing subarray addresses into selected ones of said plurality of address latches, and storing data to be written into subarray locations indicated by said subarray addresses, into selected ones of said plurality of data registers, and
- means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches.
An EEPROM chip comprising:
- a plurality of EEPROM subarrays, and
- a circuit for concurrently writing data into selected memory locations of said plurality of EEPROM subarrays, said circuit including,
- a plurality of address latches,
- a plurality of data registers individually coupled to a corresponding one of said-plurality of EEPROM subarrays,
- means for storing subarray addresses into selected ones of said plurality of address latches, and storing data to be written into subarray locations indicated by said subarray addresses,, into selected ones of said plurality of data registers, and
- means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches.
A method of concurrently writing a plurality of data chunks into an EEPROM, comprising the steps of:
- storing said plurality of data chunks into a plurality of data storage means respectively coupled to corresponding subarrays of said EEPROM;
- providing row and column select signals to row and column decoder means coupled to said corresponding subarrays of said EEPROM;
- and
- concurrently writing said plurality of data chunks stored in said plurality of data storage means into subarray locations of said corresponding subarrays of said EEPROM as indicated by said row and column select signals.
Dependencies are inferred from the claim text.