Network that transmits data in equidistant cycles

User terminal for a network wherein data is transmitted in equidistant cycles, comprising:

• a communications processor (10) that carries out the cyclic data transmission by reading the data from a memory (15) in a cyclic part of the cycle and transmitting the read data to other user terminals, or by receiving the data from other user terminals and writing this data into a memory (14);
• and
• an arithmetic unit (5, 7, 8) that accesses the memory (14, 15);
• wherein the communications processor is configured to send a synchronization signal at a fixed instant of the cycle to the arithmetic unit, and the arithmetic unit is configured to release the synchronization signal;
• wherein the user terminal is configured to block the synchronization signal after the synchronization signal has been sent and to release the synchronization signal through the arithmetic unit only if the arithmetic unit does not access the memory (14, 15) within the cyclic part;
• and
• wherein the user terminal is further configured to determine a time interval between two successive ones of the synchronization signals and to detect and signal an access without access authorization if this time interval is greater than the duration of the cycle.

A program product, comprising:

• a storage medium;
• and
• instructions that are stored on the storage medium and that are adapted to execute in a user terminal of a network in which data is transmitted in equidistant cycles, the user terminal having a communications processor and an arithmetic unit that accesses memory,
• wherein execution of the instructions causes:
• the communications processor to perform the cyclic data transmission by either or both (i) reading the data from a memory in a cyclic part (ZYK,x) of each of the cycles (Z,x) and transmitting the read data to other user terminals or (ii) receiving the data from other user terminals and writing this data into a memory;
• the communications processor to send a synchronization signal (16) at a fixed instant (Tsx) of the cycle (Z,x) to the arithmetic unit, and the arithmetic unit to release the synchronization signal;
• the synchronization signal (16) to be blocked after the synchronization signal has been sent, and the arithmetic unit to release the synchronization signal only when the arithmetic unit fails to access the memory within the cyclic part (ZYK,x);
• a time interval (ΔT′sx,x−1;
• ΔT′ex,x−1) between two successive first synchronization signals to be determined;
• and
• an access without access authorization to be detected and signaled if the time interval is greater than a duration (TDP) of the cycle (Z,x).