Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline

An arithmetic device, comprising:

• a switchable connector operable to switchingly connect data input/output lines of plural systems;
• a plurality of serial operation pipelines connected in parallel with the switchable connector;
• and
• an instruction receive mechanism operable to receive externally supplied instructions for the plurality of serial operation pipelines;
• each of the plurality of serial operation pipelines including a plurality of arithmetic-logic circuits connected in a cascade fashion, each of the arithmetic-logic circuits being operable together with other of the arithmetic-logic circuits, and
• each of the plurality of arithmetic-logic circuits including a forward line for outputting to a downstream stage data received from an upstream stage or an operation result based on the data received from the upstream stage, a backward line for feeding back to the upstream stage reverse data received from the downstream stage or an operation result based on the reverse data received from the downstream stage, a decoder for executing a process corresponding to an externally supplied instruction to produce an execution result and for outputting data representative of the execution result to a selected one of the forward and backward lines, and a latch circuit for synchronizing data output from each of the lines with respect to other of the arithmetic-logic circuits.

An arithmetic-logic circuit which is connectable in a cascade fashion as a structural element of a serial operation pipeline, the arithmetic-logic circuit comprising:

• at least one forward line for outputting to a downstream stage data received from an upstream stage of the serial operation pipeline or an operation result based on the data received from the upstream stage;
• a backward line for feeding back to the upstream stage reverse data received from the downstream stage or an operation result based on the reverse data received from the downstream stage;
• a decoder for executing a process corresponding to an externally supplied instruction to produce an execution result and for outputting data representative of the execution result to a selected one of the forward and backward lines;
• and
• a latch circuit for synchronizing data output from each of the lines with respect to another arithmetic-logic circuit.

An operation method using a serial operation pipeline, comprising:

• providing a serial operation pipeline by connecting in a cascade fashion a plurality of arithmetic-logic circuits including at least one first line for outputting data from an upstream stage to a downstream stage, and a second line for feeding back reverse data from the downstream stage to the upstream stage, each of the plurality of arithmetic-logic circuits being capable of independently conducting serial operations and selecting one of the lines to which data representative of an operation result is output;
• providing an instruction array which reflects a process of simultaneous execution through one path by the plurality of arithmetic-logic circuits, the instruction array including instructions for executing the process arranged in n rows and m columns;
• serially outputting each of the m columns of instructions to a first arithmetic-logic circuit of the serial operation pipeline;
• for each of the m columns output, executing an instruction in the column in the first arithmetic-logic circuit,
• deleting the executed instruction from the column, and
• outputting the column to a next downstream arithmetic-logic circuit;
• and
• repeating the process until all of the n rows of instructions are deleted.