Multi-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereof

A data input-processing unit comprising:

• a clock signal-receiving synchronous circuit that generates a signal-receiving internal clock as an output clock signal by phase-delaying a first clock signal by a predetermined time;
• a data input part that inputs data in sequential response to the first clock signal applied when data is applied and a second clock signal having a timing different from that of the first clock signal;
• and
• an input-processing part that processes data output from the data input part using the signal-receiving internal clock of the clock signal-receiving synchronous circuit.

A data input-processing unit comprising:

• a clock signal-receiving synchronous circuit constructed having a first delay lock loop that generates a first output clock signal by phase-delaying a first clock signal applied, when data is applied, by a predetermined time and a second delay lock loop that generates a signal-receiving internal clock as a second output clock by phase-delaying a second clock signal applied having a timing different from that of the first clock signal;
• a data input part which inputs data in sequential response to the first clock signal directly applied without passing through the clock signal-receiving synchronous circuit;
• and
• an input-processing part that processes the data output from the data input part with the first and second output clocks of the clock signal-receiving synchronous circuit.

A synchronous dynamic random access memory having a clock signal-receiving synchronous circuit for signal-receiving synchronous control formed separately from a signal-transmitting synchronous circuit, and an input circuit, the input circuit comprising:

• a first latch circuit, which latches a write data signal in response to a first clock signal applied when the write data signal is applied during a write operational mode;
• a second latch circuit, which latches the latched data output from the first latch circuit in response to a second clock signal having a timing different from the first clock signal for a signal-receiving clock conversion;
• and
• an input-processing part, which processes the latched data output from the second latch circuit in response to an output clock signal synchronously controlled on the basis of the second clock signal through the clock signal-receiving synchronous circuit.

A synchronous dynamic random access memory having a clock signal-receiving synchronous circuit for signal-receiving synchronous control formed separately from a signal-transmitting synchronous circuit, and an input circuit, the input circuit comprising:

• a first latch circuit, which latches a write data signal in response to a first clock signal applied when the write data signal is applied during a write operational mode;
• a second latch circuit, which latches the latched data output from the first latch circuit in response to a second clock signal having a timing different from the first clock signal for a signal-receiving clock conversion;
• and
• an input-processing part which processes the latched data output from the second latch circuit in response to an output clock signal synchronously controlled on the basis of the first clock signal through the clock signal-receiving synchronous circuit.

A synchronous dynamic random access memory having a clock signal-receiving synchronous circuit for signal-receiving synchronous control formed separately from a signal-transmitting synchronous circuit, and an input circuit, the input circuit comprising:

• a first latch circuit, which latches a write data signal in response to a first clock signal applied when the write data signal is applied during a write operational mode;
• a second latch circuit, which latches the latched data output from the first latch circuit in response to a second clock signal having a timing different from the first clock signal for a signal-receiving clock conversion;
• and
• an input-processing part, which processes the latched data output from the second latch circuit in response to an output clock signal synchronously controlled on the basis of the first and second clock signals through the clock signal-receiving synchronous circuit.

A synchronous dynamic random access memory having first and second delay locked loops, which perform a signal-receiving clock conversion with application of a plurality of clock domains and generate first and second output clock signals synchronously controlled on the basis of first and second clock signals applied through first and second buffers, respectively, the loops constructed separately from a signal-transmitting synchronous circuit, the loops comprising:

• a first receiver, which receives write data in response to the first output clock signal of the first delay locked loop;
• a second receiver, which receives a command in response to the second output clock signal of the second delay locked loop;
• a first latch circuit, which latches the write data received at the first receiver in response to the first clock signal applied when the write data is input;
• a second latch circuit, which latches the latched data output from the first latch circuit in response to the second clock signal having a timing different from that of the first clock signal for signal-receiving clock conversion;
• and
• an input-processing part, which input-processes the latched data output from the second latch circuit in response to the first and second output clock signals applied through the delay locked loops.