Method of forming dual damascene interconnection using low-k dielectric
AssigneeSamsung Electronics Co., Ltd.
InventorsJin-Won Jun, Young-Wug Kim, Tae-soo Park, Kyung-Tae Lee
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Abstract
A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.
Claims16
A method of forming a dual damascene interconnection, comprising:
- sequentially forming a lower insulating layer, an upper etch-stop layer, an upper insulating layer, and a hard mask layer on a semiconductor substrate where a lower conductive layer is formed;
- patterning the hard mask layer and the upper insulating layer to form an interconnection groove in the upper insulating layer, the interconnection groove exposing a portion of the upper etch-stop layer;
- forming a spacer on a sidewall of the interconnection groove;
- forming a photoresist pattern having an opening that exposes the interconnection groove and the portion of the upper etch-stop layer;
- successively etching the upper etch-stop layer and the lower insulating layer to form a hole in the lower insulating layer, the hole exposing a portion of the lower conductive layer;
- removing the patterned hard mask layer and the spacer;
- and
- forming an interconnection to fill the interconnection groove and the hole.
Dependencies are inferred from the claim text.