Methods providing oxide layers having reduced thicknesses at central portions thereof

A method of forming an integrated circuit device, the method comprising:

• forming first and second spaced apart source/drain regions on a surface of a semiconductor substrate;
• forming a gate insulating layer on the semiconductor substrate extending between the first and second spaced apart source drain regions;
• forming a gate electrode on the gate insulating layer such that the gate insulating layer is between the semiconductor substrate and the gate electrode;
• and
• after forming the gate insulating layer and forming the gate electrode on the gate insulating layer, increasing a thickness of portions of the gate insulating layer.

An integrated circuit device comprising:

• a semiconductor substrate having first and second spaced apart source/drain regions at a surface thereof;
• a gate insulating layer on the semiconductor substrate extending between the first and second spaced apart source/drain regions wherein the gate insulating layer has a reduced thickness at a central portion thereof between the first and second spaced apart source/drain regions and wherein a thickness of the gate insulating layer increases as it extends toward each of the source/drain regions;
• and
• a gate electrode on the gate insulating layer such that the gate insulating layer is between the semiconductor substrate and the gate electrode.

A method of fabricating a semiconductor device comprising:

• forming a gate oxide layer and a gate pattern on a semiconductor substrate having a cell array region and a peripheral circuit region;
• forming a source/drain region between separated portions of the gate pattern on the surface of the semiconductor substrate;
• forming an interlayer insulating film pattern for filling a gap between separated portions of the gate pattern, the interlayer insulating film having a contact hole for exposing the semiconductor substrate in the cell array region;
• increasing the thickness of the portion of the gate oxide layer in the exposed cell array region in comparison with the thickness of the gate oxide layer formed in the peripheral circuit region through oxygen diffusion by oxidizing the semiconductor substrate on the exposed cell array region;
• and
• forming a contact pad for filling the contact hole.