Etch stop layer in poly-metal structures

A method of interfacing a poly-metal stack and a semiconductor substrate by:

• forming a multi-layer poly-metal structure over said semiconductor substrate, wherein said poly-metal structure includes a patterned etch stop layer formed in a polysilicon region of said poly-metal structure;
• removing portions of said poly-metal structure extending from an upper surface of said poly-metal structure to said patterned etch stop layer to form a partial poly-metal stack including an exposed metal region along a sidewall of said stack;
• covering said exposed metal region with an oxidation barrier layer;
• removing said patterned etch stop layer to form a full poly-metal stack including an exposed oxide region along a sidewall of said stack;
• and
• interfacing said poly-metal stack and said semiconductor substrate by subjecting said exposed oxide region to an oxidation process.

A method of interfacing a poly-metal stack and a semiconductor substrate by:

• forming a multi-layer poly-metal structure over said semiconductor substrate;
• forming a patterned etch stop layer in a polysilicon region of said poly-metal structure through ion implantation;
• removing portions of said poly-metal structure extending from an upper surface of said poly-metal structure to said patterned etch stop layer to form a partial poly-metal stack including an exposed metal region along a sidewall of said stack;
• covering said exposed metal region with an oxidation barrier layer;
• removing said patterned etch stop layer to form a full poly-metal stack including an exposed oxide region along a sidewall of said stack;
• and
• interfacing said poly-metal stack and said semiconductor substrate by subjecting said exposed oxide region to an oxidation process.

A method of interfacing a poly-metal stack and a semiconductor substrate by:

• forming a multi-layer poly-metal structure over said semiconductor substrate, wherein said poly-metal structure includes a conductive etch stop layer formed in a polysilicon region of said poly-metal structure;
• removing portions of said poly-metal structure extending from an upper surface of said poly-metal structure to said etch stop layer to form a partial poly-metal stack including an exposed metal region along a sidewall of said stack;
• covering said exposed metal region with an oxidation barrier layer;
• removing portions of said etch stop layer to form a full poly-metal stack including an exposed oxide region along a sidewall of said stack;
• and
• interfacing said poly-metal stack and said semiconductor substrate by subjecting said exposed oxide region to an oxidation process.

A semiconductor structure comprising a poly-metal stack formed over a semiconductor substrate, wherein:

• a sidewall of said poly-metal stack defines a metal region, an upper polysilicon region, a lower polysilicon region, and an oxide region;
• an oxidation barrier layer covers said metal region and said upper polysilicon region;
• an oxidized layer covers said lower polysilicon region and said oxide region along said sidewall;
• and
• said oxidized layer and said oxidation barrier layer interface along said sidewall at a boundary defined between said upper and lower polysilicon regions.

A semiconductor structure comprising a poly-metal stack formed over a semiconductor substrate, wherein:

• a sidewall of said poly-metal stack includes a metal region, a polysilicon region, and an oxide region;
• an oxidation barrier layer covers said metal region and a portion of said polysilicon region;
• a portion of said polysilicon region and said oxide region define an oxidized layer along said sidewall;
• a conductive etch stop layer is formed in said polysilicon region of said poly-metal stack;
• said oxidized layer and said oxidation barrier layer interface along said sidewall at a point defined by said conductive etch stop layer.

A memory cell array comprising an array of wordlines and digitlines arranged to access respective memory cells within said array, wherein:

• respective ones of said wordlines comprise a poly-metal stack formed over a semiconductor substrate;
• a sidewall of said poly-metal stack defines a metal region, an upper polysilicon region, a lower polysilicon region, and an oxide region;
• an oxidation barrier layer covers said metal region and said upper polysilicon region;
• an oxidized layer covers said lower polysilicon region and said oxide region along said sidewall;
• and
• said oxidized layer and said oxidation barrier layer interface along said sidewall at a boundary defined between said upper and lower polysilicon regions.

A computer system comprising a memory cell array in communication with a microprocessor via a data communication path, wherein:

• said memory cell array comprises an array of wordlines and digitlines arranged to access respective memory cells within said array;
• respective ones of said wordlines comprise a poly-metal stack formed over a semiconductor substrate;
• a sidewall of said poly-metal stack defines a metal region, an upper polysilicon region, a lower polysilicon region, and an oxide region;
• an oxidation barrier layer covers said metal region and said upper polysilicon region;
• an oxidized layer covers said lower polysilicon region and said oxide region along said sidewall;
• and
• said oxidized layer and said oxidation barrier layer interface along said sidewall at a boundary defined between said upper and lower polysilicon regions.

A method of providing operational uniformity across a multi-memory cell semiconductive device, said method comprising:

• providing a semiconductor substrate;
• forming a first oxide layer on said semiconductor substrate;
• forming an polysilicon layer on said oxide layer;
• forming a barrier layer on said polysilicon layer;
• forming a metal layer on said barrier layer;
• forming a second oxide layer on said metal layer;
• providing a masking layer over portions of said second oxide layer;
• implanting ions into said polysilicon layer to form at least one etch stop layer;
• etching said substrate to said etch stop layer, said portions covered by said masking layer defining poly-metal structures on said oxide layer, said poly-metal structure includes a metal region, a polysilicon region, and an oxide region;
• forming an oxidation barrier layer on exposed portions of said metal region and said polysilicon region;
• etching said substrate to said oxide layer adjacent said poly-metal structures;
• and
• oxidizing said substrate such that an oxidized layer forms on a remaining exposed portion of said polysilicon region, said oxide barrier layer and said oxidized layer define sidewalls, and said oxidized layer and said oxidation barrier layer interface along said sidewalls at a point defined by said conductive etch stop layer.