Method for fabricating dram cell transistor having trench isolation structure

Abstract

The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion of a field oxide film, which is caused by the reduction in the potential barrier between a junction region and a channel region, which is caused because the channel doping concentration at the edge portion of the field oxide film is lowered due to a boron segregation effect caused by the field oxide film, as compared to the central portion of a channel region. According to the method of the present invention, an electrode structure having the same conductive type as that of a well region is formed within the field oxide film. Thus, a back bias is applied to the well region, and at the same time, also applied to the electrode formed within the field oxide film, so that the electric potential at the edge portion of the field oxide film is increased and the potential barrier between the junction region and the channel region is increased, thereby improving the punch-through characteristic.

Dependencies are inferred from the claim text.