SOI device with reduced junction capacitance
AssigneeInternational Business Machines Corporation
InventorToshiharu Furukawa
Life of this patent
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Abstract
An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.
Claims29
A semiconductor structure comprising:
- a dielectric layer, said dielectric layer having a first and a second region, said first region having a first dielectric constant and said second region having a second dielectric constant different from said first dielectric constant.
An SOI FET comprising:
- a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region, said undoped region having a dielectric constant different from a dielectric constant of said doped regions;
- source/drains in said silicon layer and separated by a body in said silicon layer, said source/drains aligned over said doped regions and said body aligned over said undoped region;
- and a gate dielectric on top of said body and a gate on top of said gate dielectric.
A method of fabricating a semiconductor structure comprising:
- providing a dielectric layer;
- forming a first region in said dielectric layer, said first region having a first dielectric constant;
- and forming a second region in said second dielectric, said second region having a second dielectric constant different from said first dielectric constant.
A method of fabricating an SOI FET comprising:
- providing a silicon substrate having silicon layer on top of a buried oxide layer;
- forming a gate dielectric on top of silicon layer;
- forming a gate conductor on top of said gate dielectric;
- forming source/drains in said silicon layer;
- said source drains separated by a body in said silicon layer, said body aligned under said gate;
- and forming doped regions in said buried oxide layer, said doped regions aligned under said source/drains and having a dielectric constant different from a dielectric constant of non-doped regions of said buried oxide layer.
Dependencies are inferred from the claim text.