High performance sub-system design and assembly

An interchip interface circuit formed in multiples upon a plurality of integrated circuit chips for communication between internal circuits of the plurality of integrated circuit chips;

• whereby said plurality of integrated circuit chips are attached physically and electrically to one another;
• and
• whereby each interchip interface circuit comprises:
• an internal interface circuit for transferring electrical signals between a one of said integrated circuit chips to another of said integrated circuit chips;
• a mode select switch having a first terminal connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry said one of said integrated circuit chips, a third terminal connected to I/O circuits, and a control terminal;
• and
• a mode selector connected to the control terminal to selectively connect the output of the internal interface circuit to the internal circuitry of said one of said integrated circuit chips during multi-chip operation and the output of the internal interface circuit to I/O interface circuitry during single chip operation.

A method of forming a multiple integrated circuit chip structure comprising the steps of:

• simultaneously but separately forming internal circuits on a plurality of semiconductor wafers containing a plurality of integrated circuit chips;
• simultaneously forming input/output circuits on said plurality of semiconductor wafers;
• simultaneously forming interchip interface circuits on said plurality of semiconductor wafers, whereby forming said interchip interface circuit comprises the steps of:
• forming an internal interface circuit for transferring electrical signals between each of said plurality of integrated circuit chips to each other of said integrated circuit chips;
• forming a mode select switch having a first terminal connected to an output of the internal interface circuit and a second terminal connected to the internal circuitry of one of said plurality of integrated circuit chips;
• forming a mode selector to selectively connect the output of the internal interface circuit to the internal circuitry of said one of said integrated circuit chips during multi-chip operation and the output of the internal interface circuit to the input/output circuits during single chip operation;
• during single chip operation, contacting, stimulating, and examining a response of test circuits connected to said input/output circuitry and input/output interface circuits on the said plurality of wafers;
• separating said plurality of semiconductor wafers into a plurality of separated integrated circuit chips;
• contacting with sockets, stimulating and burning-in the plurality of separated integrated circuit chips for an extended period of time;
• contacting, stimulating, and examining the plurality of separated integrated circuit chips;
• discarding defective integrated circuit chips;
• attaching each functioning chip of one of said semiconductor wafers to one or more functioning chips of one or more of other of said plurality of semiconductor wafers;
• and
• contacting the input/output interface circuits, stimulating, and examining the response of the formed multiple integrated circuit chip structure.