US 2003/0199117 A1Published application

Method for fabricating array substrate for x-ray detector

AssigneeLG.Philips LCD Co., Ltd.

InventorKeuk-Sang Kwon

Life of this patent

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Abstract

An array substrate for use in an X-ray sensing device is fabricated using an etching stopper that enables good control of the etching process and that prevents over-etch of drain electrodes and second capacitor electrodes while forming contact holes and a cutting furrow. The etching stopper is located in a tiling portion that is utilized for tiling substrates to form a large-sized X-ray detector. During fabrication, gate lines can have gate-protruded portions located near the etching stopper, and the etching stopper can have stopper-protruded portions near the gate lines. The stopper-protruded portions electrically connect to the gate-protruded portions through gate line contact holes such that the etching stopper and the gate lines have equipotentials. This can reduce static electricity damage.

Claims20

Dependent claims

A method of fabricating an array substrate, comprising:

forming a gate line, having a gate electrode and a gate pad, on a substrate;
forming a first insulation layer on the gate line, on the gate electrode, on the gate pad and on the substrate;
forming an active layer on the first insulation layer and over the gate electrode;
forming source and drain electrodes, a data line and a ground line, wherein the source and drain electrodes extend over the active layer, wherein the data line is electrically connected to the source electrode, wherein the data line and the gate line define a pixel region, and wherein the ground line crosses the pixel region;
forming a first capacitor electrode and a first etching stopper, wherein the first capacitor electrode electrically contacts the ground line, and wherein the first etching stopper is over a portion of the gate line;
forming a protection layer on the thin film transistor, on the first capacitor electrode, and on the first etching stopper;
forming a second capacitor electrode on the protection layer and over the first capacitor electrode;
forming a second insulation layer on the protection layer and on the second capacitor electrode;
and
forming a cutting furrow to the first etching stopper by etching the second insulation layer and the protection layer.

7 more elements

An array substrate comprising:

a plurality of gate lines on a substrate, each gate line having at least one gate electrode and a gate-protruded portion;
a first insulation layer over the gate lines, over the gate electrodes, over the gate protruded portions, and over the substrate;
a plurality of gate line contact holes, each passing through said first insulation to said gate-protruded portions;
a conductive shorting element having a plurality of stopper-protruded portions that electrically connect to the gate lines via the gate-protruded portions, wherein said conductive shorting element electrically connects said plurality of gate lines together, and wherein said conductive shorting element is comprised of a conductive material;
a plurality of thin film transistors on said first insulation layer, each thin film transistor located over a gate electrode and having a source electrode, a drain electrode, an ohmic contact layer, and a channel region in an active layer;
a plurality of drain electrodes, each contacting an ohmic contact layer of an associated thin film transistor;
a plurality of data lines on said first insulation layer, each data line having a plurality of source electrodes that electrically contact to a plurality of ohmic contact layers, wherein said plurality of data lines cross said plurality of gate lines to define a plurality of pixel regions;
a ground line under each pixel region, said ground line being on said first insulation layer;
a first capacitor electrode over said ground line and over a portion of said first insulation layer, said first capacitor electrode electrically connecting to said ground line, wherein said first capacitor electrode is comprised of said conductive material;
a protection layer over said thin film transistor, over said data lines, over said source electrodes, over said drain electrodes, over said conductive shorting element, and over said first capacitor electrode;
a plurality of second capacitor electrodes on said protection layer and over said first capacitor electrodes;
a second insulating layer over said protection layer and over said second capacitor electrodes;
and
a cutting furrow through said second insulating layer and through said protection layer to said conductive shorting element.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/436,070Filed 13 May 2003
Priority: KR 1999-6785031 Dec 1999
Published: 23 Oct 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10F 39/189
Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors: x-ray, gamma-ray or corpuscular radiation imagers
H10F 39/014
Manufacture or treatment of image sensors covered by group H10F39/12: of CMOS image sensors
H10F 39/026
Manufacture or treatment of image sensors covered by group H10F39/12: wafer-level processing
H10F
Solar cells and light sensors

Family

Application09/750,074Division · filed 29 Dec 2000
Application10/436,070Division · filed 13 May 2003
US 2002/0076861 A1Published application
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US 2003/0199117 A1This patent

From the US filing history. Foreign family members aren’t listed.