Copper wiring module control

A copper wiring module for processes wafers, said copper wiring module comprising:

• a plating tool for applying a plating to a wafer;
• a first metrology device for measuring plating wafer property information during or after processing by the plating tool;
• a polishing tool for polishing the wafer via at least one copper removal step;
• a second metrology device for measuring plating wafer property information during or after processing by the polishing tool;
• and
• a controller for optimizing processing of the polishing tool by using at least one of said plating wafer property information received from said first metrology device and said polishing wafer property information received from said second metrology device to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.

An optimizer for optimizing processing of a copper wiring module, said optimizer comprising:

• a communications port for receiving plating wafer property information received from a first metrology device associated with a plating tool and polishing wafer property information received from a second metrology device associated with a polishing tool;
• a memory for storing tool recipes used to control operation of said plating tool and said polishing tool;
• and
• a controller for optimizing processing of said polishing tool by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of a polishing tool recipe to obtain a desired output property on a wafer.

A system for controlling an output property during wafer processing in a copper wiring module, said system comprising:

• means for measuring plating wafer property information during or after processing by a plating process;
• means for feeding said plating wafer property information to a polishing process, said polishing process comprising at least one copper removal step;
• means for measuring polishing wafer property information during or after processing by said polishing process;
• and
• means for optimizing said polishing process by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.

An optimizer for optimizing processing of a copper wiring module, said optimizer comprising:

• means for receiving plating wafer property information received from a first metrology device associated with a plating tool and polishing wafer property information received from a second metrology device associated with a polishing tool;
• means for storing tool recipes used to control operation of said plating tool and said polishing tool;
• and
• means for optimizing processing of said polishing tool by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of a polishing tool recipe to obtain a desired output property on a wafer.

A computer readable medium for controlling an output property during wafer processing in a copper wiring module, said computer readable medium comprising:

• computer readable instructions for measuring plating wafer property information during or after processing by a plating process;
• computer readable instructions for feeding said plating wafer property information to a polishing process, said polishing process comprising at least one copper removal step;
• computer readable instructions for measuring polishing wafer property information during or after processing by said polishing process;
• and
• computer readable instructions for optimizing said polishing process by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.