DC-tolerant bit slicer and method
AssigneeWireless Interface Technologies, Inc.
InventorBang-Sup Song
Life of this patent
Estimating the term…
Abstract
A bit slicer circuit and method detect the peak of the differential slope in a demodulated data signal received via a wireless data system, so that bit slicing can be insensitive to DC fluctuations. This is accomplished by detecting when the demodulated signal transitions by more than a predetermined threshold value Vth during each symbol period, and determining the polarity of a detected transition. A latch is set and a logic “1”, is output when the polarity of a detected transition is negative; the latch is reset and a logic “0” is output when the polarity is positive.
Claims23
A DC-tolerant bit slicer suitable for detecting digital data contained within a demodulated signal received via a wireless data system having a predetermined symbol period D, comprising:
- a slope level threshold detector which receives a demodulated signal via a wireless data system and detects whether said received signal transitions by more than a predetermined threshold value Vth during each of said symbol periods,
- a slope polarity detector which detects the polarity of a transition detected by said slope level threshold detector, and
- a latch which is set when said slope level threshold detector detects a transition and said slope polarity detector detects that the polarity of said transition is negative and is reset when said slope level threshold detector detects a transition and said slope polarity detector detects that the polarity of said transition is positive.
A DC-tolerant bit slicer suitable for detecting digital data contained within a demodulated signal received via a wireless data system having a predetermined symbol period D, comprising:
- a slope level threshold detector which receives a demodulated signal via a wireless data system and detects whether said received signal transitions by more than a predetermined threshold value Vth during each of said symbol periods,
- a differentiator arranged to differentiate the output of said slope level threshold detector to determine the polarity of a transition detected by said slope level threshold detector,
- a comparator connected to the output of said differentiator, said comparator having an output which toggles from a first state to a second state when the output of said differentiator crosses zero, and
- a first latch which is set when said slope level threshold detector detects a transition, said differentiator determines that the polarity of said transition is negative, and said comparator output toggles from a first state to a second state, and is reset when said slope level threshold detector detects a transition, said differentiator detects that the polarity of said transition is positive, and said comparator output toggles from a first state to a second state.
The bit slicer of claim 17, said delay circuit further comprising:
- a first analog delay cell interposed between said demodulated signal and said delay circuit input, said first analog delay cell comprising a first switch connected to receive said demodulated signal, a first capacitor which is connected to said demodulated signal when said first switch is closed, and a first buffer amplifier which is connected to said first capacitor at an input and which produces an output to said delay circuit's input, said first switch operated with a clock which is in-phase with clock phase Φx1, and
- a final delay cell interposed between said delay cells' outputs and said delay circuit's output, said final delay cell comprising a capacitor connected to the outputs of each of said n analog delay cells and a buffer amplifier connected at its input to said capacitor and which produces said delay circuit's output at its output, said first analog delay cell and said final delay cell arranged to facilitate timing synchronization.
A method for detecting digital data contained within a demodulated signal received via a wireless data system having a predetermined symbol period D, comprising:
- detecting, during each of said symbol periods, when a received demodulated signal transitions by more than a predetermined threshold value Vth,
- detecting the polarity of each detected transition, and
- outputting a logic “1”, when a detected transition has a negative polarity and outputting a logic “0” when a detected transition has a positive polarity.
Dependencies are inferred from the claim text.