Frequency converter

A converter circuit for performing transfer of control signals between one first device (2) and one second device (3) coming under an interconnection bus, said first device (2) operating according to a first clock signal (clock_1) at a first frequency and said second device (3) operating according to a second clock signal (clock_2) at a second frequency, said clock frequencies being possibly in a first ratio to one another corresponding to unity, as well as in a second and a third ratio, and in which said control signals comprise:

• an access-request signal (req_1, req_2) to be transferred from said first device (2) to said second device (3);
• a grant signal (gnt_1, gnt_2) to be transferred from said second device (3) to said first device (2);
• and
• a response-to-request signal (r_req_1, r_req_2) to be transferred from said second device (3) to said first device (2), characterized in that the converter circuit comprises:
• manipulation circuit elements (28, 30 and 32) which identify respective propagation paths through the converter circuit (4) for said access-request signal (req_1, req_2), said grant signal (gnt_1, gnt_1), and said response-to-request signal (r_req_1, r_req_2);
• and
• a logic network (34 to 42) which can assume three states, corresponding, respectively, to said first, second and third ratios between the frequencies of said clock signals (clock_1, clock_2), interposing selectively manipulation elements (28, 30, 32) in said propagation paths, the arrangement being such that:
• a) when the logic network is in the first state corresponding to said ratio of unity between the frequencies, said manipulation elements (28, 30 and 32) are uncommitted by said propagation paths, so that said access-request signal (req_1, req_2), said grant signal (gnt_1, gnt_2), and said response-to-request signal (r_req_1, r_req_2) propagate through the converter circuit (4) in substantial absence of manipulation.
• b) when said logic network comes to be in said second state corresponding to said second ratio between the frequencies, the manipulation elements (28, 30 and 32) are interposed in said propagation paths, in such a way that:
• said request signal (req_1, req_2) is selectively delayed in the transfer through the converter circuit (4) according to the logic levels assumed by said first clock signal (clock_1) and by said second clock signal (clock_2) at the instant of the request (A, C);
• said grant signal (gnt_1, gnt_2) is delayed in traversing the converter circuit (4) according to the logic levels assumed by said first clock signal (clock_1) and by said second clock signal (clock_2) at the instant of grant signalling (A, C, D1, D3);
• and
• the response-to-request signal (r_req_1, r_req_2) is delayed in traversing the converter circuit (4) according to the logic levels assumed by said first clock signal (clock_1) and by said second clock signal (clock_2) at the instant of response (A, F;
• D1, D3) so as to prevent a violation of the set-up time, said response-to-request signal (r_req_1, r_req_2) being likewise shortened in time;
• and
• c) when said logic network (34 to 42) comes to be in said third state corresponding to said third ratio between the frequencies, said manipulation elements (28 to 32) are uncommitted by the propagation path of said request signal (req_1, req_2), so that said request signal propagates through the converter circuit (4) in substantial absence of manipulation;
• said grant signal (gnt_1, gnt_2) is subjected to delay in propagation through the converter circuit (4);
• and
• said response-to-request signal (r_req_1, r_req_2) is shortened in time in traversing the converter circuit (4) in order to prevent its double sampling by said first device (2);
• the arrangement being such that the converter operates at the maximum possible frequency in the absence of latency.