Semiconductor memory device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorNaoki Kuroda
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes: a memory cell configured with two transistors and one capacitor; two word drivers for controlling two word lines alternately, the two word lines controlling reading/writing with respect to the memory cell; two address latch circuits for latching a first address signal to select one of the word drivers, the two address latch circuits being respectively provided upstream from the two word drivers; and an address decoder for decoding a second address signal to generate the first address signal. In this device, the address decoder supplies the first address signal in common to both of the two address latch circuits.
Claims10
A semiconductor memory device comprising:
- a memory cell comprising two transistors and one capacitor;
- two word drivers for controlling two word lines alternately, the two word lines controlling reading/writing with respect to the memory cell;
- two address latch circuits for latching a first address signal to select the two word drivers, the two address latch circuits being respectively provided upstream from the two word drivers;
- and
- an address decoder for decoding a second address signal to generate the first address signal,
- wherein the address decoder supplies the first address signal in common to both of the two address latch circuits.
Dependencies are inferred from the claim text.