Simultaneous function dynamic random access memory device technique

Abstract

A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“DRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock cycle. The technique of the present invention is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the advantages of the technique are obtained through the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.

Dependencies are inferred from the claim text.