Semiconductor memory device equipped with refresh timing signal generator
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTsukasa Hagura, Takafumi Takatsuka, Masaki Tsukude
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Abstract
A semiconductor memory device such as a pseudo SRAM or the like is provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. A selector selects a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal, and a signal generator changes the refresh period according to a number of blocks selected by said selecting means, and generates a refresh timing signal having a changed refresh period and outputs a generated refresh signal.
Claims5
A semiconductor memory device comprising:
- a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit;
- selecting means for selecting a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal;
- and
- signal generating means for changing the refresh period according to a number of blocks selected by said selecting means and generating a refresh timing signal having a changed refresh period, and outputting a generated refresh signal.
A semiconductor memory device comprising:
- a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit;
- setting means for setting whether or not data is held at only a predetermined block in the memory cell array divided into a plurality of blocks, in accordance with a predetermined first command signal;
- frequency dividing means for dividing a frequency of the refresh timing signal by a predetermined frequency division number in accordance with a predetermined second command signal, and outputting a frequency-divided refresh timing signal;
- and
- signal selecting means for outputting the frequency-divided refresh timing signal outputted from said frequency dividing means in place of the undivided refresh timing signal, when said setting means performs setting so that data is held at only the predetermined block in said memory cell array.
Dependencies are inferred from the claim text.