System and method for quick self-refresh exit with transitional refresh

A self-refresh control system directing a DRAM device having a plurality of rows of memory cells during a self-refresh mode, the self-refresh control system comprising:

• a self-refresh clock issuing a self-refresh clock signal;
• a row refreshing circuit, receptive of the self-refresh clock signal, the row refreshing circuit directing a refresh of a row of memory cells in response to the self-refresh clock signal;
• and
• a transitional refresh controller receptive of a refresh signal and a self-refresh transition signal, the refresh signal indicating when a row is being refreshed and the self-refresh transition signal indicating when a computing system directs the DRAM device to transition between a self-refresh mode and an operational mode, the transitional refresh controller initiating a refresh of at least one row of memory cells when the self-refresh exit signal indicates the computing system is directing the DRAM device to transition between the self-refresh mode and the operational mode, and the refresh signal does not indicate a row is presently being refreshed.

A DRAM device comprising:

• a plurality of rows of DRAM memory cells;
• a row addressing system operably connected to the DRAM array, the row addressing system responsive to a row address signal by accessing a row in the DRAM array corresponding to the row address signal;
• a self-refresh clock issuing a self-refresh clock signal;
• a row refreshing circuit, operably connected with the row addressing system and the plurality of rows of DRAM memory cells, the row refreshing circuit directing a refresh of at least one row of memory cells in response to one of the self-refresh clock signal;
• a refresh signal indicating when a row of memory cells is being refreshed by the row refreshing circuit;
• a self-refresh transition signal indicating when a computing system is directing the DRAM device to transition between self-refresh mode and an operational mode;
• and
• a transitional refresh controller receptive of a refresh signal and a self-refresh transition signal, the refresh signal indicating when a row is being refreshed and the self-refresh transition signal indicating when a computing system directs the DRAM device to transition between a self-refresh mode and an operational mode, the transitional refresh controller initiating a refresh of at least one row of memory cells when the self-refresh exit signal indicates the computing system is directing the DRAM device to transition between the self-refresh mode and the operational mode, and the refresh signal does not indicate a row is presently being refreshed.

A computer system, comprising:

• a processor;
• an input device, operably connected to the processor, allowing data to be entered into the computer system;
• an output device, operably connected to the processor, allowing data to be output from the computer system;
• and
• a system memory operably connected to the processor, comprising a plurality of DRAM devices, the DRAM devices comprising a row addressing system operably connected to the DRAM array, the row addressing system responsive to a row address signal by accessing a row in the DRAM array corresponding to the row address signal;
• a self-refresh clock issuing a self-refresh clock signal;
• a row refreshing circuit, operably connected with the row addressing system and the plurality of rows of DRAM memory cells, the row refreshing circuit directing a refresh of at least one row of memory cells in response to one of the self-refresh clock signal and an immediate refresh signal;
• and a transitional refresh controller receptive of a refresh signal and a self-refresh transition signal, the refresh signal indicating when a row is being refreshed and the self-refresh transition signal indicating when a computing system directs the DRAM device to transition between a self-refresh mode and an operational mode, the transitional refresh controller initiating a refresh of at least one row of memory cells when the self-refresh exit signal indicates the computing system is directing the DRAM device to transition between the self-refresh mode and the operational mode, and the refresh signal does not indicate a row is presently being refreshed;
• and
• a data path coupled to an external data terminal of the DRAM array.

A method for transitioning a DRAM device having a plurality of rows of memory cells between self-refreshing and operating, comprising:

• detecting when a row is being refreshed;
• detecting when a computing system directs the DRAM device to transition between refreshing itself and operating;
• and
• initiating a refresh of at least one row of memory cells upon detecting the computing system is directing the DRAM device to transition between self-refreshing and operating when no row is being refreshed.