Proportional to temperature voltage generator
AssigneeCypress Semiconductor Corporation
InventorTimothy E. Fiscus
Life of this patent
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Abstract
A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in response to changes in temperature.
Claims20
A biasing circuit comprising:
- a first circuit configured to generate a first bias signal and a second bias signal, wherein said second bias signal is defined by a threshold voltage and a first resistance;
- and
- a second circuit configured to generate a third bias signal in response to said first and second bias signals and a second resistance, wherein said third bias signal has a magnitude that is linearly proportional to absolute temperature (PTAT) and is configured to vary a refresh rate of a memory cell in response to changes in temperature.
A circuit for generating temperature sensitive biasing of a voltage controlled oscillator (VCO) comprising:
- a first circuit configured to generate a first bias signal and a second bias signal, wherein said second bias signal is defined by a threshold voltage and a first resistance;
- and
- a second circuit configured to generate one or more third bias signals in response to said first and second bias signals and a second resistance, wherein said one or more third bias signals have a magnitude that is linearly proportional to absolute temperature (PTAT) and vary a refresh rate of a memory cell with temperature.
A method for controlling a refresh rate of a memory using a proportional to absolute temperature (PTAT) voltage reference comprising the steps of:
- (A) generating a first bias signal;
- (B) generating a second bias signal in response to said first bias signal, wherein said second bias signal is defined by a threshold voltage and a first resistance;
- and
- (C) generating a third bias signal in response to said first and second bias signals and a second resistance, wherein said third bias signal has a magnitude that is linearly proportional to absolute temperature (PTAT)and is configured to vary a refresh rate of a memory cell with temperature.
Dependencies are inferred from the claim text.