Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier

A method of operating a semiconductor memory, the method comprising:

• reading from and writing to addressable locations of the semiconductor memory under control of a program executing on a processor coupled thereto;
• and
• performing an in-situ test operation and, responsive to failure indication consistent with an accumulated data-dependent disparity between operating characteristics of opposing devices of a sensing circuit, increasing latency of a sensing circuit control signal to accommodate the disparity.

A method of compensating for accumulated data-dependent post-manufacture creep in a characteristic of one or more devices of a sensing circuit of a semiconductor memory, the method comprising:

• performing an in-situ test operation that writes data to and reads data from at least selected elements of the semiconductor memory;
• and
• varying latency in a control signal path leading to the sensing circuit to achieve identity between the written and read data, the latency variation at least partially compensating for the characteristic mismatch.

An integrated circuit comprising:

• a sensing circuit susceptible to an accumulated data-dependent post-manufacture creep in a characteristic of a device thereof, the characteristic creep affecting optimal timing of the sensing circuit;
• and
• a variable delay element introducible in a timing path coupled to the sensing circuit, the variable delay element responsive to an operating symptom of the characteristic creep.

An integrated circuit chip that compensates for disparate accumulated data-dependent post-manufacture creep in a characteristic of opposing devices of a sense amplifier at least in part by varying a latency of a sense amplifier control signal.

A computer readable encoding of a semiconductor integrated circuit design, the computer readable encoding comprising:

• one or more media encoding a representation of a memory circuit that includes plural pairs of bit lines, memory cells coupled to respective ones of the bit line pairs, and sense amplifiers coupled to one or more respective ones of the bit line pairs;
• the one or more media further encoding a representation of at least one variable delay circuit coupled into a control signal path of one or more respective ones of the sense amplifiers, the variable delay circuit responsive to a signal indicative of an accumulated data-dependent mismatch in characteristics of the opposing devices of at least one of the respective sense amplifiers to at least partially compensate for the characteristic mismatch by varying latency of a sensing operation of the sense amplifier.

An apparatus comprising:

• means for sensing a differential pair in a semiconductor memory;
• means for varying delay of a sensing operation of the sensing means, the variable delay means responsive to an accumulated data-dependent mismatch in characteristics of opposing devices of the sensing means, wherein the variable delay means, when employed, at least partially compensates for the characteristic mismatch.