6F2 DRAM array with apparatus for stress testing an isolation gate and method

A DRAM array including:

• a first memory cell;
• a second memory cell;
• and
• an isolation gate formed between the first and second memory cells and configured to provide electrical isolation therebetween;
• and
• a first transistor having first and second load electrodes and a control electrode configured to accept a control signal, the first load electrode being coupled to the isolation gate and the second load electrode being configured to be coupled to a stress voltage.

A method of forming memory cells in a 6F2 DRAM array including:

• forming a first memory cell;
• forming a second memory cell adjacent the first memory cell;
• forming an isolation gate between the first and second memory cells and configured to provide electrical isolation therebetween;
• and
• forming a first switch having first and second load electrodes and a control electrode configured to accept a control signal, the first load electrode being coupled to the isolation gate and the second load electrode being configured to be coupled to a stress voltage.

A method of stress testing an isolation gate formed between two rows of memory cells in a DRAM array comprising:

• ensuring that a first switch coupled between the isolation gate and a first potential is OFF;
• toggling a second switch coupled between the isolation gate and a stress potential ON;
• waiting for a predetermined interval;
• toggling the second switch OFF;
• toggling the first switch ON;
• and
• performing function testing of the DRAM array.

A method of isolating a single row of memory cells in a 6F2 DRAM array comprising:

• providing pairs of rows of memory cells;
• providing an isolation gate separating rows comprising each pair of rows, each isolation gate being configured to isolate one of the pair of rows from another of the pair of rows;
• and
• providing a transistor having a load electrode coupled to the isolation gate, the transistor being configured to supply a suitable voltage to the isolation gate to isolate one of the pair of rows from another of the pair of rows in response to a control signal.

A computer system comprising:

• a central processing unit;
• an input interface coupled to the central processing unit;
• and
• a memory device coupled to the central processing unit, the memory device storing instructions and data for use by the central processing unit, wherein the memory device includes a DRAM array including:
• a first memory cell;
• a second memory cell;
• an isolation gate formed between the first and second memory cells and configured to provide electrical isolation therebetween;
• and
• a first transistor having first and second load electrodes and a control electrode configured to accept a control signal, the first load electrode being coupled to the isolation gate and the second load electrode being configured to be coupled to a voltage source.