Clock recovery circuit and data receiving circuit

A data receiving circuit comprising:

• a data discrimination circuit discriminating data in an input signal in accordance with a data discrimination clock;
• a boundary detection circuit detecting a boundary in said input signal in accordance with a boundary detection clock;
• a phase control code generating circuit generating a phase control code by receiving outputs from said data discrimination circuit and said boundary detection circuit;
• a boundary detection timing varying circuit dynamically varying boundary detection timing in said boundary detection circuit by applying a variation to said boundary detection phase control code;
• and
• a variation reducing circuit reducing a phase variation occurring in said data discrimination clock in accordance with the dynamic variation of said boundary detection timing performed by said boundary detection timing varying circuit.

A data receiving circuit comprising:

• a data discrimination clock generating circuit generating a data discrimination clock by receiving a first phase control code of a first bit count;
• a data discrimination circuit discriminating data in an input signal in accordance with said data discrimination clock;
• a boundary detection circuit detecting a boundary in said input signal in accordance with a boundary detection clock;
• a phase control code generating circuit generating a second phase control code of a second bit count which is larger than said first bit count, by receiving outputs from said data discrimination circuit and said boundary detection circuit;
• and
• an addition processing circuit adding a prescribed variation pattern varying to said second phase control code, and thereby outputting said first phase control code corresponding to said first bit count, wherein said data discrimination clock generating circuit generates the data discrimination clock whose phase is controlled with a resolution equivalent in effect to said second bit count.

A data receiving circuit comprising:

• a data discrimination circuit discriminating data in an input signal in accordance with a data discrimination clock;
• a boundary detection circuit detecting a boundary in said input signal in accordance with a boundary detection clock;
• a phase control code outputting means for outputting a phase control signal by receiving outputs from said data discrimination circuit and said boundary detection circuit;
• and
• a clock generating circuit generating said data discrimination clock and said boundary detection clock by receiving said phase control signal, wherein said clock generating circuit generates said data discrimination clock and said boundary detection clock by using a plurality of feedback loops having different signal delays.

A data receiving circuit comprising:

• a data discrimination circuit discriminating data in an input signal in accordance with a data discrimination clock;
• a boundary detection circuit detecting a boundary in said input signal in accordance with a boundary detection clock;
• a phase control code outputting means for outputting a phase control signal by receiving outputs from said data discrimination circuit and said boundary detection circuit;
• and
• a clock generating circuit generating said data discrimination clock and said boundary detection clock by receiving said phase control signal, and wherein:
• a fixed clock derived from a system reference clock is supplied to a feedback loop for generating said data discrimination clock and said boundary detection clock.