Non-volatile semiconductor memory device
AssigneeSeiko Epson Corporation
InventorsTeruhiko Kamei, Masahiro Kanai
Life of this patent
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Abstract
A non-volatile semiconductor device in which the number of redundant cells is not increased in proportion to the number of simultaneously accessed bits, having a redundant cell layout which prevents an increase in access time. This non-volatile semiconductor memory device has a regular cell array in which a plurality of memory cells are arranged. The regular cell array is divided into N sector regions in the row direction. Each of the N sector regions is divided into n first memory blocks in the row direction. One of the n first memory blocks is a redundant memory block. The (n−1) first memory blocks correspond to (n−1) input/output terminals.
Claims12
A non-volatile semiconductor memory device comprising:
- a regular cell array in which a plurality of memory cells are arranged in a column direction and a row direction, each of the memory cells having first and second non-volatile memory cells that are controlled by one word gate and first and second control gates, wherein:
- the regular cell array is divided in the row direction into N sector regions;
- each of the N sector regions is divided in the row direction into n first memory blocks;
- and
- one of the n first memory blocks is a redundant memory block including a plurality of redundant memory cells.
Dependencies are inferred from the claim text.