Word line selector for a semiconductor memory
AssigneeSTMicroelectronics S.r.l.
InventorFederico Pio
Life of this patent
Estimating the term…
Abstract
A word line selector for selecting word lines of an array of semiconductor memory cells formed in a doped semiconductor region of a semiconductor substrate comprises a plurality of word line drivers responsive to word line selection signals. Each word line driver is associated with a respective word line for driving the word line to prescribed word line electric potentials, depending on an operation to be conducted on the array of memory cells, in accordance with the word line selection signal.
Claims28
A word line selector for selecting word lines of an array of semiconductor memory cells formed in a doped semiconductor region of a semiconductor substrate, comprising a plurality of word line drivers responsive to word line selection signals, each word line driver being associated with a respective word line for driving the word line to prescribed word line electric potentials according to the word line selection signals, said word line electric potentials depending on an operation to be conducted on the array of memory cells, characterized in that a plurality of distinct doped semiconductor well structures is provided in the semiconductor substrate, each doped semiconductor well structure accommodating a respective group of at least one word line driver associated with a respective group of at least one word line.
A memory circuit, comprising:
- a first plurality of semiconductor well structures that are electrically isolated from one and other;
- and
- a plurality of word-line drivers each disposed in a respective one of the well structures.
A method for erasing a nonvolatile memory cell, the method comprising:
- driving to a first voltage a first semiconductor well structure that includes a word-line driver for the memory cell;
- and
- driving to a second voltage a second semiconductor well structure that includes a word-line driver for another memory cell.
A method for erasing a nonvolatile memory cell, the method comprising:
- driving to a first voltage a first semiconductor region that includes a first transistor for driving the memory cell;
- driving to a second voltage a second semiconductor region that includes a second transistor for driving the memory cell;
- driving to a third voltage a third semiconductor region that includes a third transistor for driving another memory cell;
- and
- driving to a fourth voltage a fourth semiconductor region that includes a fourth transistor for driving the other memory cell.
A method for erasing a first nonvolatile memory cell, the method comprising:
- driving to a first voltage a first semiconductor region that includes a first transistor for driving the first memory cell and that includes a second transistor for driving a second memory cell in a same group as the first memory cell;
- driving to a second voltage a second semiconductor region that includes a third transistor for driving the first memory cell and that includes a fourth transistor for driving the second memory cell;
- driving to a third voltage a third semiconductor region that includes a fifth transistor for driving a third memory cell that is in a different group from the first memory cell;
- driving to a fourth voltage a fourth semiconductor region that includes a sixth transistor for driving the third memory cell;
- driving a gate of the first memory cell to a fifth voltage with the third transistor;
- driving a gate of the second memory cell to a sixth voltage with the second transistor;
- and
- driving a gate of the third memory cell to a seventh voltage with the fifth transistor.
Dependencies are inferred from the claim text.