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AssigneeHitachi, Ltd.
InventorsToru Matsushita, Hideaki Kurata, Naoki Kobayashi
Estimating the term…
Disclosed herewith is a method for controlling the operation of non-volatile semiconductor chips with high sequential access performance realized by smoothing out the variation of the times for writing, erasing, and reading data in/from memory cells among sectors in each of the chips. To realize the above method, a write command is inputted to each of a plurality of non-volatile semiconductor memory chips simultaneously in the first step, the same addresses are specified in the plurality of non-volatile semiconductor memory chips simultaneously in the second step, and one of the plurality of non-volatile semiconductor memory chips is selected in the third step. Then, a data block and a write start command are inputted to the selected non-volatile semiconductor memory chip. This operation is repeated for each memory chip selected sequentially in the third step. And, in the fourth step, the end of the write start command processing is determined in each chip and the command execution result is checked therein separately. When data is to be written in a plurality of different addresses, the write command input and the address input in and after the second round are done to each memory chip separately.
A writing controlling method used by memory controlling means to divide data into a plurality of data blocks and storing said data blocks in a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
An erasing controlling method used by memory controlling means to erase data from a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
An erasing controlling method used by memory controlling means to erase data from a plurality of non-volatile memory chips connected through a common bus, said method comprising:
A reading controlling method used by memory controlling means to read a plurality of data blocks stored in a plurality of non-volatile memory chips connected through a common bus, said method comprising:
A reading controlling method used by memory controlling means to read a plurality of data blocks stored in the same addresses specified in a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
A writing controlling method used by memory controlling means to divide data into a plurality of data blocks and store said data blocks in a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
A writing controlling method used by memory controlling means to divide data into a plurality of data blocks and store said data blocks in a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
An erasing controlling method used by memory controlling means to erase data from a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
An erasing controlling method used by memory controlling means to erase data from a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
A reading controlling method used by memory controlling means to read a plurality of data blocks stored in a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
A reading controlling method used by memory controlling means to read a plurality of data blocks stored in the same addresses specified in a plurality of non-volatile semiconductor memory chips connected to a common bus, said method comprising:
Dependencies are inferred from the claim text.