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AssigneeSamsung Electronics Co., Ltd.
InventorJong-Yeol Park
Estimating the term…
A refresh circuit having a variable restore time according to an operating mode of a semiconductor memory device and a refresh method of the same is provided. The refresh circuit includes a refresh pulse generating unit for receiving a clock signal to generate first and second refresh signals, a standby refresh signal generating unit for receiving the second refresh signal and a chip select signal to generate a standby refresh signal, the chip select signal representing an active state and a standby state of the semiconductor memory device, and a word-line pulse generating unit for receiving the first refresh signal and the standby refresh signal to generate a word-line driving signal. A pulse width of the word-line driving signal generated at the standby state is longer than that generated at the active state resulting in a sufficient refresh time at each memory cell.
A refresh circuit for a semiconductor memory device comprising:
A refresh circuit for a semiconductor memory device comprising:
A method for refreshing a semiconductor memory device, the method comprising the steps of:
Dependencies are inferred from the claim text.
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Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
Control and timing of internal memory operations: standby or low power modes
Static stores
Term end not estimated
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a refresh circuit having a variable restore time according to an operating mode of a semiconductor memory device and a refresh method of the same.
2. Discussion of the Related Art
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
FIG. 1 is a block diagram of a refresh circuit in accordance with an embodiment of the present invention;
FIG. 2 is a circuit diagram of the self-refresh oscillator shown in FIG. 1;
Hereinafter, a refresh circuit contained in a semiconductor memory device and a refresh method of the same will be described in detail.
FIG. 1 is a block diagram of a refresh circuit 100 in accordance with an embodiment of the present invention. Referring to FIG. 1, the refresh circuit 100 of the present invention includes a self-refresh oscillator 200, a refresh pulse generating unit 300, a standby refresh signal generating unit 400 and a word-line pulse generating unit 500. The self-refresh oscillator 200 generates a clock signal POSC having a predetermined period. The refresh pulse generating unit 300 receives the clock signal POSC to generate first and second refresh signals RFHTD and PRFH. The standby refresh signal generating unit 400 receives the second refresh signal PRFH and a chip select signal CSb to generate a standby refresh signal CS_RFHb. The word-line pulse generating unit 500 receives the first refresh signal RFHTD and the standby refresh signal CS_RFHb to generate a word-line driving signal PWL.
FIG. 2 is a circuit diagram of the self-refresh oscillator 200 shown in FIG. 1. Referring to FIG. 2, the self-refresh oscillator 200 includes an inverter chain unit 210 and a buffer unit 260. The inverter chain unit 210 is provided with an odd numbers of inverter, which include a first inverter 220, a second inverter 240 and a third inverter 250. The inverter chain unit 210 further includes a delay unit 270 coupled between the first inverter 220 and the third inverter 250.