Semiconductor memory

#1. Field of the Invention

#The present invention relates to semiconductor memories that have volatile memory cells each having a capacitor and that have interfaces as of SRAMs.

#2. Description of the Related Art

#The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:

#FIG. 1 is a block diagram showing a first embodiment of the present invention;

#FIG. 2 is a block diagram showing the details of the arbiter of FIG. 1;

#Embodiments of the present invention will be described below with reference to the drawings.

#FIG. 1 shows a first embodiment of semiconductor memory according to the present invention. In the figure, each of the signal lines shown by thick lines is constituted by a plurality of bits. Double circles shown on the left side of the figure designate external input terminals. The signals identified by designations prefixed with “/” represent negative logics, while the signals identified by designations postfixed with “Z” represent positive logics. In the following descriptions, signals may be referred to by using their respective abbreviations; for example, “external clock signal CLK” may be referred to as “CLK signal”, and “chip enable signal /CE” may be referred to as “/CE signal”.

#This semiconductor memory is formed as a pseudo SRAM having memory cells as of a DRAM and also having interfaces as of an SRAM. This pseudo SRAM has a refresh control circuit 10, an arbiter 12, a command decoder 14, a burst control circuit 16, a mode setting control circuit 18, a burst address counter 20, a timing control circuit 22, an address latch 24, an address decoder 26, a memory cell array 28, a read/write amplifier 30, a burst transfer register 32, a data output control circuit 34, and a data input control circuit 36.