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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakashi Kono
Estimating the term…
A preamplifier includes an amplifier circuit amplifying a signal level of read data, a latency shifter outputting the read data onto a data line pair in response to an internal signal determining a timing of outputting the read data onto the data bus pair, and a driver outputting the read data onto the data bus pair. The amplifier circuit receives the internal signal and outputs the read data onto the data line pair while bypassing the latency shifter when the internal signal is already at high level at the timing when the signal level of the read data is amplified. As a result, a semiconductor memory device can speed up propagation of the read data from the preamplifier onto the data bus pair in a high frequency operation.
A semiconductor memory device allowing data input/output in synchronization with a rise and a fall of an external clock, comprising:
Dependencies are inferred from the claim text.
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Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: i/O lines read…
Read-write [R-W] circuits: input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
Term end not estimated
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device operating at high frequencies in synchronization with a rise and a fall of an external clock and including a preamplifier amplifying data read from a memory cell array to be output to a data bus pair.
2. Description of the Background Art
FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor memory device in accordance with the present invention.
FIG. 2 is a functional block diagram functionally illustrating a circuit configuration from a bit line pair to a data bus pair in the semiconductor memory device in accordance with the present invention.
FIG. 3 is a first circuit diagram showing a circuit configuration of an amplifier circuit shown in FIG. 2.
In the following, an embodiment of the present invention will be described with reference to the figures. It is noted that in the figures the same or corresponding parts will be denoted with the same reference characters and therefore description thereof will not be repeated.
FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor memory device 10 in accordance with the present invention.
Referring to FIG. 1, semiconductor memory device 10 includes a clock terminal 12, a control signal terminal 14, an address terminal 16, a data input/output terminal 18 and a data strobe signal input/output terminal 20.