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AssigneeMacronix International Co., Ltd.
InventorsKuang-Wen Liu, Chong-Jen Huang, Jui-Lin Lu
Estimating the term…
The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.
A method for forming a memory device, comprising:
A memory device comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Read-only memory [rom] devices
Read-only memory [ROM] devices: peripheral circuit regions
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
Arrangements for protection of devices: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
Term end not estimated
1. Field of the Invention
The invention relates to a memory device and manufacturing method thereof and, more particularly, to a memory device with a shielding metal layer over a memory cell area, and manufacturing method thereof.
2. Description of the Related Art
FIG. 1 is a schematic diagram showing a memory device in accordance with an embodiment of the invention;
FIG. 2 is a schematic diagram showing a memory substrate of the memory device shown in FIG. 1; and
FIGS. 3A to 3C are schematic diagrams showing steps for forming the memory device in accordance with the embodiment of the invention.
The memory device and manufacturing method thereof in accordance with a preferred embodiment of the invention will be described with reference to the accompanying drawings, wherein the same reference numbers denote the same elements.
Referring to FIG. 1, a memory device 1 in accordance with an embodiment of the invention includes a memory substrate 11, an insulating layer 12, a shielding metal layer 13, a second dielectric layer 14 and a second metal layer 15.
In this embodiment, the memory substrate 11 includes a substrate 111, a memory cell area 112, a peripheral circuit area 113, a first dielectric layer 114 and a first metal layer 115. The memory cell area 112 and the peripheral circuit area 113 are formed on the substrate 111, the first dielectric layer 114 is formed on the memory cell area 112 and peripheral circuit area 113, and the first metal layer 115 is formed on the first dielectric layer 114. Those skilled in the art should know that the memory cell area 112 has a plurality of memory cells and the memory cells are electrically connected to a plurality of word lines and a plurality of bit lines, respectively. Besides, the word lines and bit lines are constituted by metal layers of the memory device 1 (including the first metal layer 115 and the second metal layer 15). Since the circuit design of the memory cells and the metal layers is well-known to those skilled in the art, description thereof is omitted here. The peripheral circuit area 113 is used to control access to each of the memory cells. The first dielectric layer 114 can be an inter-layer dielectric layer (ILD). A plurality of contact holes 116 are formed in the first dielectric layer 114. Therefore, the first metal layer 115 can be electrically connected to the memory cell area 112 and the peripheral circuit area 113 through the contact holes 116, so as to form a circuit layout in accordance with a desired design.