Multi-port memory cell

#The invention relates generally to the field of circuit design, and in particular to an improved multi-port memory cell.

#In super-scalar, Very Long Instruction Word (VLIW) processors and in network processors memory cells with multiple write ports are typically required. These multiple write ports are associated with multiple bit lines, that allow both writing the same data to many memory cells as well as allowing direct communication paths from the multiple execution units to one memory cell.

#Prior art multi-port register memory cells used a single write word line for each differential write bit line or a differential write word line for each single write bit line. Using differential word or bit lines caused a large line count which in turn increased the layout area for the memory cell.

#FIG. 1 is schematic of an example of a prior art multi-write port memory cell;

#FIG. 2 shows a conventional final decoding circuit of the prior art, applicable to FIG. 1;

#FIG. 3 is a schematic of a multi-write port memory cell of an embodiment of the present invention;

#In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It is apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention.

#The circuit of FIG. 1 may be viewed as a single six input multiplexer (bit lines BLA to BLF) with six selector lines (word lines WLA to WLF), where a “multiplexer,” as used herein, is a circuit for selecting one of a number of inputs and switching its information to the output or outputs. In FIG. 1, each word line selects the associated bit line, for example, word line WLA selects bit line BLA. In order to reduce the number of word lines one preferred embodiment of the present invention uses a plurality of smaller cascaded multiplexers with each word line now selecting one or more bit lines.

#FIG. 3 is a schematic of a multi-write port memory cell of an embodiment of the present invention. Circuit 300 has five word lines, i.e., WLAB, WLCD, WLEF, WLBDF, and WLACE, and six bit lines, i.e., BLA, BLB, BLC, BLD, BLE, and BLF. The letters following “WL” in the word line labels were picked to indicate in the alternative which bit line may be selected, when the word line is asserted. For example, when word line WLAB is asserted, then either bit line BLA or BLB may be selected, or when word line WLBDF is asserted, then either bit line BLB, BLD, or BLF may be selected. Word line WLAB is connected to the gates of transistors m3 and m4. Word line WLCD is connected to the gates of transistors m2 and m5. Word line WLEF is connected to the gates of transistors m1 and m6. Word line WLBDF is connected to the gates of transistors m7 and m11. The gate of transistor m7 is connected to transistors m4, m5, and m6 via node n1. Transistor m7is also connected to node n4. Transistor m11 is connected to transistor m12 and to node n3. The gate of the transistor m12 is connected to transistors m4, m5 and m6 via node 1. Word line WLACE is connected to the gates of transistors m8 and m10. The gate of transistor m8 is connected to transistors m1, m2, and m3 via node n2. The gate of transistor m8 is also connected to node n4. Transistor m10 is connected to transistor m9. The gate of transistor m9 is connected to transistors m4, m5, and m6 via node n2. Back-to-back inverters Inv1 and Inv2 form the one bit memory cell. The output of inverter Inv1 is connected to the input of inverter Inv2 via node n3. The output of inverter Inv2 is connected to the input of inverter Inv1 via node n4. Bit line BLE is connected to transistor m1. Bit line BLC is connected to transistor m2. Bit line BLA is connected to transistor m3. Bit line BLB is connected to transistor m4. Bit line BLD is connected to transistor m5. Bit line BLF is connected to transistor m6.