Fully hidden refresh dynamic random access memory

A semiconductor memory device comprising:

• a plurality of memory cells arranged in rows and columns;
• a row address transition detection circuit for detecting a transition in a row address signal for designating a row of the memory cells and generating a row address transition detection signal;
• a column address transition detection circuit for detecting a transition in a column address signal designating a column of the memory cells and generating a column address transition detection signal;
• an array activating signal generating circuit for generating an array activating signal for alternatively activating and inactivating a memory cell selecting operation in response to said row address transition detection signal;
• and
• a column selection control signal generating circuit for generating a column selection activating signal for activating an operation of selecting a column of the memory cells in response to activation of either of said array activating signal and said column address transition detection signal.

A semiconductor memory device comprising:

• a plurality of memory cells;
• an address transition detection circuit for detecting a transition in an address signal for designating an address of a memory cell in said plurality of memory cells and generating an address transition detection signal in a one-shot pulse form;
• a pulse width change circuit for changing a pulse width of the address transition detection signal for outputting;
• and
• a cell selection control signal generating circuit for generating a cell selection control signal for controlling an operation of selecting a memory cell in the memory cells in response to an output signal of said pulse width change circuit.