US 2003/0198089 A1 · Semiconductor storage device

Abstract

A semiconductor storage device in the invention comprises a first control transistor which is connected between a bit line and a first node and whose control terminal is connected to a word line, a data retention circuit which includes a first transistor that is connected between the first node and a second reference voltage terminal, as well as a first inverter that includes a second transistor connected between a second node and the second reference voltage terminal, and a substrate potential control circuit which selectively alters a substrate potential of the first transistor so as to make a threshold voltage of the first transistor higher as compared with threshold voltages of the first control transistor and the second transistor. Thus, it is permitted to provide the semiconductor storage device of static type which realizes a reduced layout area and a lower-dissipation-power operation while ensuring the reliability and high operating speed of the write and read of data.

Drawings

Drawings are temporarily unavailable. Open the PDF at USPTO

Drawings

Claims24

Dependent claims

A semiconductor storage device comprising:

a first reference voltage terminal which supplies a first potential that is a predetermined logic level;
a second reference voltage terminal which supplies a second potential that is lower than the first potential, and that is a logic level different from the predetermined logic level;
a first node;
a first control transistor which is connected between a bit line and said first node, and whose control terminal is connected to a word line;
a data retention circuit which includes a first transistor that is connected between said first node and said second reference voltage terminal, and that has its control terminal connected to a second node, and a first inverter that includes a second transistor connected between said second node and said second reference voltage terminal, having its input terminal connected to said first node, having its output terminal connected to the control terminal of said first transistor, and outputting to said output terminal a voltage correspondent to the logic level different from the logic level inputted to said input terminal;
and
a substrate potential control circuit which selectively alters a substrate potential of said first transistor so as to make a threshold voltage of said first transistor higher as compared with threshold voltages of said first control transistor and said second transistor.

4 more elements

A semiconductor storage device comprising:

a first reference voltage terminal which supplies a first potential that is a predetermined logic level;
a second reference voltage terminal which supplies a second potential that is lower than the first potential, and that is a logic level different from the predetermined logic level;
a first node;
a first control transistor which includes a first channel region connected between a bit line and said first node, and whose control terminal is connected to a word line;
and
a data retention circuit which includes a first transistor that includes a second channel region connected between said first node and said second reference voltage terminal, and that has its control terminal connected to a second node, and a first inverter that includes a second transistor including a third channel region connected between said second node and said second reference voltage terminal, having its input terminal and its output terminal respectively connected to said first node and to the control terminal of said first transistor, and outputting to said output terminal a voltage correspondent to the logic level different from the logic level inputted to said input terminal;
wherein an impurity concentration of the second channel region is higher as compared with impurity concentrations of the first and third channel regions.

4 more elements

A semiconductor storage device comprising:

a first reference voltage terminal which supplies a first potential that is a predetermined logic level;
a second reference voltage terminal which supplies a second potential that is lower than the first potential, and that is a logic level different from the predetermined logic level;
a first node;
a first control transistor which is connected between a first bit line and said first node, and whose control terminal is connected to a word line;
a second node;
a second control transistor which is connected between a second bit line and said second node, and whose control terminal is connected to the word line;
a data retention circuit which includes a first inverter that includes a first transistor connected between said first node and said second reference voltage terminal, and having its control terminal connected to said second node, and that outputs to said first node a voltage correspondent to the logic level different from the logic level inputted to said second node, and a second inverter that includes a second transistor connected between said second node and said second reference voltage terminal, and having its control terminal connected to said first node, and that outputs to said second node a voltage correspondent to the logic level different from the logic level inputted to said first node;
wherein the threshold voltage of said first transistor in case of writing data into said first node is higher as compared with threshold voltages of said first control transistor and said second transistor.

5 more elements

Dependencies are inferred from the claim text.

Description7,966 words

Summary1,479 words

#The present invention relates to a static random access memory (SRAM) which is a semiconductor storage device, and more particularly to a semiconductor storage device of low power dissipation which has a high integration degree and which performs a high-speed operation.

#In general, a memory cell in a prior-art SRAM is constructed of bit lines BL and BLb which pair with each other, a data retention circuit which includes a first CMOS inverter that is constituted by a first P-channel type MOS transistor (hereinbelow, termed “PMOS”) connected to a first node N1 and a supply potential Vdd, as well as a first N-channel type MOS transistor (hereinbelow, termed “NMOS”) connected to the first node N1 and a ground potential Vbb, and a second CMOS inverter that is constituted by a second PMOS connected to a second node N2 and the supply potential Vdd, as well as a second NMOS connected to the second node N2 and the ground potential Vbb, that is operated by receiving the output of the first CMOS inverter and that delivers its output as the input of the first CMOS inverter, and a first or second control transistor which is connected to a word line WL and which renders the path between the bit line BL or BLb and the first or second node N1 or N2 electrically conductive or nonconductive.

#That is, the memory cell in the prior-art SRAM is constructed of the six MOS (Metal Oxide Semiconductor) transistors.

Brief description of the drawings6 figures

#While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:

#FIG. 1 is a circuit diagram showing a semiconductor storage device in a first embodiment of the invention;

#FIG. 2 is a circuit diagram showing a practicable example of a substrate potential control circuit in the first embodiment of the invention;

Detailed description6,318 words

#Now, the first embodiment of the invention will be described in detail with reference to the drawings.

#FIG. 1 is a diagram showing a semiconductor storage device in the first embodiment of the invention, while FIG. 2 is a diagram showing a practicable example of a substrate potential control circuit in this embodiment.

#The semiconductor storage device in this embodiment is constructed of pluralities of bit lines and word lines, and a plurality of memory cells which are connected to the intersection points between the bit lines and the word lines. One of the memory cells is concretely shown in FIG. 1.

Semiconductor storage device

Life of this patent

Semiconductor storage device

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims24

Description7,966 words

Drawings

Classification2 codes

Life of this patent

Description7,966 words