Low voltage single poly deep sub-micron flash EEPROM

A method of erasing an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first injector region and said second injector region;
• and
• (b) grounding said control gate region and said semiconductor substrate;
• and
• (c) applying no bias voltage to said drain region, wherein said drain region is electrically floating;
• and
• (d) applying a bias voltage of a first polarity to said source region.

A method of reading an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector regions, and applying a bias voltage of said first polarity to said control gate region;
• and
• (b) applying a bias voltage of said first polarity to said drain region;
• and
• (c) grounding said source region and said semiconductor substrate.

A method of programming an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a first control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region and a second control gate region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector regions of said first capacitive device, and applying a bias voltage of said first polarity to said first control gate region;
• and
• (b) applying a bias voltage of a second polarity to said third and fourth injector regions of said second capacitive device, and grounding said second control gate region;
• and
• (c) applying a positive bias voltage or electrically floating said drain region and source region of said transistor device;
• and
• (d) grounding said semiconductor substrate.

A method of erasing an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a first control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region and a second control gate region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first and second injector region of said first capacitive device, and grounding said first control gate region;
• and
• (b) applying a bias voltage of said second polarity or electrically floating said third and fourth injector regions of said second capacitive device, and grounding said second control gate region;
• and
• (c) applying a bias voltage of a first polarity to said source region and electrically floating said drain region;
• and
• (d) grounding said semiconductor substrate.

A method of reading an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a first control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region and a second control gate region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector regions of said first capacitive device and applying a bias voltage of said first polarity to said first control gate region ;
• and
• (b) applying a bias voltage of said first polarity to said third and fourth injector regions of said second capacitive device and applying a bias voltage of said first polarity to said second control gate region;
• and
• (c) applying a bias voltage of said first polarity to said drain region and grounding said source region;
• and
• (d) grounding said semiconductor substrate.

A method of programming an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector regions of said first capacitive device, and applying a bias voltage of said first polarity to said control gate region;
• and
• (b) applying a bias voltage of a second polarity to said third and fourth injector regions of said second capacitive device;
• and
• (c) applying a positive bias voltage or electrically floating said drain region and source region of said transistor device;
• and
• (d) grounding said semiconductor substrate.

A method of erasing an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first and second injector region of said first capacitive device, and grounding said control gate region;
• and
• (b) applying a bias voltage of said second polarity or electrically floating said third and fourth injector regions of said second capacitive device;
• and
• (c) applying a bias voltage of a first polarity to said source region and electrically floating said drain region;
• and
• (d) grounding said semiconductor substrate.

A method of reading an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector regions of said first capacitive device and applying a bias voltage of said first polarity to said control gate region;
• and
• (b) applying a bias voltage of said first polarity to said third and fourth injector regions of said second capacitive device;
• and
• (c) applying a bias voltage of said first polarity to said drain region and grounding said source region;
• and
• (d) grounding said semiconductor substrate.

A method of programming an EEPROM memory cell, said cell comprising a transistor device formed on a semiconductor substrate, wherein said transistor includes a first source region, a second source region and a drain region;

• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector region, and applying a bias voltage of said first polarity to said control gate region;
• and
• (b) applying a bias voltage of said first polarity to said drain region;
• and
• (c) grounding said second source region and said semiconductor substrate;
• and
• (d) applying no bias voltage to said first source region, so that said first source region is electrically floating.

A method of erasing an EEPROM memory cell, said cell comprising a transistor device formed on a semiconductor substrate, wherein said transistor includes a first source region, a second source region and a drain region;

• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first injector region and said second injector region;
• and
• (b) grounding said control gate region and said semiconductor substrate;
• and
• (c) applying no bias voltage to said drain region and said second source region, whereby said drain region and said second source region are electrically floating;
• and
• (d) applying a bias voltage of a first polarity to said first source region.

A method of reading an EEPROM memory cell, said cell comprising a transistor device formed on a semiconductor substrate, wherein said transistor includes a first source region, a second source region and a drain region;

• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector region, and applying a bias voltage of said first polarity to said control gate region;
• and
• (b) applying a bias voltage of a first polarity to said drain region;
• and
• (c) grounding said second source region and applying no bias voltage to said first source region, whereby said first source region is electrically floating or grounding said first source region and applying no bias voltage to said second source region, whereby said second source region is electrically floating
• (d) grounding said semiconductor substrate.

A method of programming an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region within a graded diffusion region, a drain region within a graded diffusion region which includes a contact region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector region, and applying a bias voltage of said first polarity to said control gate region;
• and
• (b) applying a bias voltage of a second polarity to said drain region ;
• and
• (c) applying a positive bias voltage to said contact region;
• and
• (d) grounding said source region and said semiconductor substrate.

A method of erasing an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region within a graded diffusion region, a drain region within a graded diffusion region which includes a contact region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first injector region and said second injector region;
• and
• (b) grounding said control gate region and said semiconductor substrate region;
• and
• (c) applying no bias voltage to said drain region and said contact region, whereby said drain region and contact region are electrically floating;
• and
• (d) applying a bias voltage of a first polarity to said source region.

A method of reading an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region within a graded diffusion region, a drain region within a graded diffusion region which includes a contact region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a control gate region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector region, and applying a bias voltage of said first polarity to said control gate region;
• and
• (b) applying a bias voltage of a first polarity to said contact region ;
• and
• (c) applying no bias voltage to said drain region, whereby said drain region is electrically floating;
• and
• (d) grounding said source region and said semiconductor substrate.

A method of programming an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a first control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region, a first and second diffusion region, a fifth and sixth injector region and a third and fourth diffusion region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector regions of said first capacitive device, and applying a bias voltage of said first polarity to said first control gate region;
• and
• (b) applying a bias voltage of a second polarity to said third, fourth, fifth and sixth injector regions of said second capacitive device;
• and
• (c) applying a bias voltage of a first polarity to said first, second, third and fourth diffusion regions of said second capacitive device;
• and
• (d) applying a positive bias voltage or electrically floating said drain region and source region of said transistor device;
• and
• (e) grounding said semiconductor substrate.

A method of erasing an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a first control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region, a first and second diffusion region, a fifth and sixth injector region and a third and fourth diffusion region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first and second injector regions of said first capacitive device, and grounding or electrically floating said first control gate region;
• and
• (b) applying a bias voltage of a second polarity to said third, fourth, fifth and sixth injector regions of said second capacitive device;
• and
• (c) grounding or electrically floating said first, second, third and fourth diffusion regions of said second capacitive device;
• and
• (d) applying a positive bias voltage to said source region and electrically floating said drain region of said transistor device;
• and
• (e) grounding said semiconductor substrate.

A method of reading an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a first control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region, a first and second diffusion region, a fifth and sixth injector region and a third and fourth diffusion region, the method comprising:
• (a) applying a bias voltage of a first polarity to said first and second injector regions of said first capacitive device, and applying a bias voltage of said first polarity to said first control gate region;
• and
• (b) applying a bias voltage of a first polarity to said third, fourth, fifth and sixth injector regions of said second capacitive device;
• and
• (c) applying a bias voltage of a first polarity to said first, second, third and fourth diffusion regions of said second capacitive device;
• and
• (d) applying a bias voltage of a first polarity to said drain region;
• and
• (e) grounding said source and said semiconductor substrate.

A method of erasing an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a first control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region and a second control gate region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first and second injector region of said first capacitive device, and grounding said first control gate region;
• and
• (b) applying a bias voltage of said first polarity to said third injector region, said fourth injector region and said second control gate of said second capacitive device;
• and
• (c) electrically floating said source region and said drain region;
• and
• (d) grounding said semiconductor substrate.

A method of erasing an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region;
• and a control gate region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first and second injector region of said first capacitive device;
• and
• (b) applying a bias voltage of said first polarity to said third and fourth injector region of said second capacitive device;
• and
• (c) applying a bias voltage of said first polarity to said control gate or grounding said control gate region;
• and
• (d) electrically floating said source region and said drain region;
• and
• (e) grounding said semiconductor substrate.

A method of erasing an EEPROM memory cell, said cell comprising:

• a transistor device formed on a semiconductor substrate, wherein said transistor includes a source region, and a drain region;
• and
• a first capacitive device, wherein said first capacitive device includes a first and second injector region and a first control gate region;
• and
• a second capacitive device wherein said capacitive device includes a third and fourth injector region, a first and second diffusion region, a fifth and sixth injector region and a third and fourth diffusion region, the method comprising:
• (a) applying a bias voltage of a second polarity to said first and second injector regions of said first capacitive device, and grounding or electrically floating said first control gate region;
• and
• (b) applying a bias voltage of a first polarity to said third, fourth, fifth and sixth injector regions of said second capacitive device;
• and
• (c) applying a bias voltage of a first polarity to said first, second, third and fourth diffusion regions of said second capacitive device;
• and
• (d) electrically floating said drain region and source region of said transistor device;
• and
• (e) grounding said semiconductor substrate.