Semiconductor integrated circuit device and a method of manufacturing the same

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate, and includes a first gate electrode disposed near one memory electrode on said channel region with an insulating film interposed between said first gate electrode and said channel region, and a second gate electrode disposed near the other memory electrode on said channel region with an insulating film and a charge storage region interposed between said second gate electrode and said channel region and electrically isolated from said first gate electrode, and
• wherein said access circuit is capable of selecting a first state in which a first negative voltage is applied to said first well region to thereby apply a reverse voltage between said memory electrode near said second gate electrode and said first well region and to apply a voltage for forming an electric field for directing a first polarity charge from said well region side to said charge storage region to said second gate electrode, and a second state in which a voltage for forming an electric field for directing a second polarity charge to said charge storage region is applied to said second gate electrode and said first well region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate, and includes a first gate electrode disposed near a region for one memory electrode on said channel region with an insulating film interposed between said first gate electrode and said channel region, and a second gate electrode disposed near a region for the other memory electrode on said channel region with an insulating film and a charge storage region interposed between said second gate electrode and said channel region and electrically isolated from said first gate electrode, and
• wherein said access circuit is capable of selecting a first operation in which a negative voltage for forming a reverse bias state between said second gate electrode and said memory electrode near said second gate electrode is applied to said first well region to thereby inject a first polarity charge into said charge storage region, and a second operation in which a positive voltage is applied to said second gate electrode to thereby inject a second polarity charge into said charge storage region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor;
• a first MIS transistor relatively thin in gate insulating film;
• and
• a second MIS transistor relatively thick in gate insulating film, said memory cell transistor, said first MIS transistor and said second MIS transistor being provided on a semiconductor substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate, and includes a first gate electrode disposed near a region for one memory electrode on said channel region with an insulating film interposed between said first gate electrode and said channel region, and a second gate electrode disposed near a region for the other memory electrode on said channel region with an insulating film and a charge storage region interposed between said second gate electrode and said channel region and electrically isolated from said first gate electrode, and is capable of storing information different according to a difference between amounts of a first polarity charge and a second polarity charge injected into the charge storage region,
• wherein said insulating film placed below the first gate electrode is substantially equal to said gate insulating film of said first MIS transistor in thickness,
• wherein said well region is supplied with a negative voltage for forming a reverse bias state between said second gate electrode and said memory electrode near said second gate electrode when said first polarity charge is injected into said charge storage region, and
• wherein said second gate electrode is supplied with a positive voltage when said second polarity charge is injected into said charge storage region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate, and includes, over said channel region, memory gate electrodes separately disposed near said respective memory electrodes through insulating films and charge storage regions, and a control gate electrode disposed between both said memory gate electrodes with an insulating film interposed therebetween and electrically isolated from said memory gate electrodes, and
• wherein said access circuit is capable of selecting a first state in which a negative voltage is applied to the first well region to form a reverse bias state between said well region and said one memory electrode and to form an electric field for directing a first polarity charge from said well region side to said charge storage region on said one memory electrode side, a second state in which an electric field for directing a second polarity charge from said well region to said charge storage regions of both said memory gate electrodes is formed, and a third state in which a current is allowed to mutually flow from said one memory electrode to said other memory electrode through said channel region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate and includes, over said channel region, memory gate electrodes separately disposed near said respective memory electrodes through insulating films and charge storage regions, and a control gate electrode disposed between both said memory gate electrodes with an insulating film interposed therebetween and electrically isolated from said memory gate electrodes, and
• wherein said access circuit is capable of selecting a first operation in which a negative voltage is applied to said first well region to thereby form a reverse bias state between said first well region and said one memory electrode and inject a first polarity charge into said one charge storage region, a second operation in which a positive voltage is applied to both said memory gate electrodes to thereby inject a second polarity charge from said well region to both said charge storage regions, and a third operation in which a current is allowed to mutually flow from said one memory electrode to said other memory electrode through said channel region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor;
• a first MIS transistor relatively thin in gate insulating film;
• and
• a second MIS transistor relatively thick in gate insulating film, said memory cell transistor, said first MIS transistor and said second MIS transistor being provided on a semiconductor substrate,
• wherein said memory cell transistor includes a source region, a drain region and a channel region interposed between said source region and said drain region, which are provided within a first well region of said semiconductor substrate, and includes a first gate electrode disposed on one sides of the source region and drain region, a second gate electrode disposed on the other sides of said source region and drain region, a first gate insulating film formed between said channel region and said first gate electrode, a charge storage region formed between said channel region and said second gate electrode, and an insulating film for electrically isolating said first gate electrode from said second gate electrode, which are provided over said channel region, and
• wherein upon a write or erase operation of the memory cell transistor, a negative voltage having a value smaller in absolute value than one equal to several times a power voltage of a circuit comprising said first MIS transistor, and a ground voltage for said circuit are applied to said first well region to thereby inject carriers into said charge storage region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor;
• a first MIS transistor relatively thin in gate insulating film;
• and
• a second MIS transistor relatively thick in gate insulating film, said memory cell transistor, said first MIS transistor and said second MIS transistor being provided on a semiconductor substrate,
• wherein said memory cell transistor includes a source region, a drain region, a channel region interposed between said source region and said drain region, a gate electrode, and a charge storage region formed between said channel region and said gate electrode, which are provided within a first well region of said semiconductor substrate, and
• wherein upon a write or erase operation of said memory cell transistor, a negative first voltage is applied to said gate electrode, a negative second voltage not greater than the first voltage in absolute value is applied to said first well region, and a third voltage not greater in absolute value than a power voltage of a circuit comprised of said first MIS transistor is applied to said source or drain region to thereby inject holes into said charge storage region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor;
• and
• a peripheral circuit transistor,
• wherein said memory cell transistor includes, in a memory cell forming region of a semiconductor substrate, a source region, a drain region, a channel region interposed between said source region and said drain region, a first gate electrode and a second gate electrode disposed on said channel region, a first gate insulating film formed between said channel region and said first gate electrode, a charge storage region formed between said channel region and said second gate electrode, and an insulating film for electrically isolating said first gate electrode from said second gate electrode,
• wherein said peripheral circuit transistor has a gate electrode over a peripheral circuit transistor forming region of said semiconductor substrate, and
• wherein said gate electrode of said peripheral circuit transistor comprises a film formed by laminating a first conductive film lying in the same layer as said first gate electrode, and a second conductive film lying in the same layer as said second gate electrode.

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

• forming a first conductive film over a memory cell forming region and a peripheral circuit transistor forming region of a semiconductor substrate;
• patterning said first conductive film lying over the memory cell forming region to form a first conductive pattern which serves as a first gate electrode of a memory cell and leaving said first conductive film over said peripheral circuit transistor forming region;
• forming a second conductive film over said memory cell forming region and said first conductive film in said peripheral circuit transistor forming region;
• and
• etching said second conductive film to form each second gate electrode of said memory cell on at least side walls of said first conductive pattern, and forming a gate electrode of each peripheral circuit transistor comprising said second conductive film and first conductive film over said peripheral circuit transistor forming region.

A semiconductor integrated circuit device comprising:

• a memory cell,
• wherein said memory cell includes a source region, a drain region, and a channel region interposed between said source region and said drain region, which are provided within a semiconductor region, and includes a first gate electrode, a second gate electrode, and an insulating film for electrically isolating said first gate electrode from said second gate electrode, which are provided over said channel region,
• wherein said channel region comprises a first channel region and a second channel region,
• wherein a first gate insulating film is provided between said first channel region and said first gate electrode,
• wherein a second gate insulating film is provided between said second channel region and said second gate electrode,
• wherein said second gate electrode is formed higher than said first gate electrode, and
• wherein a silicide layer for said second gate electrode and a silicide layer for said first gate electrode are electrically isolated by sidewall spacers, each comprised of an insulating film, which are formed in self-alignment with side walls of said second gate electrode.

A semiconductor integrated circuit device comprising:

• a memory cell,
• wherein said memory cell includes a source region, a drain region, and a channel region interposed between said source region and said drain region, which are provided within a semiconductor region, and includes a first gate electrode, a second gate electrode, and an insulating film for electrically isolating said first gate electrode from said second gate electrode, which are provided over said channel region,
• wherein said channel region comprises a first channel region and a second channel region,
• wherein a first gate insulating film is provided between said first channel region and said first gate electrode,
• wherein a second gate insulating film is provided between said second channel region and said second gate electrode,
• wherein said second gate electrode is formed on side walls of the first gate electrode through an insulating film in sidewall spacer form,
• wherein a thickness of said second gate electrode is thicker than a thickness of said first gate electrode, and
• wherein a height on a substrate surface, of said second gate electrode is higher than a height on said substrate surface, of said first gate electrode.

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

• forming a first conductive film over a memory cell forming region of a semiconductor substrate and forming an insulating film over said first conductive film;
• etching said insulating film and said first conductive film to form a first conductive pattern which serves as a first gate electrode of a memory cell;
• forming a second gate electrode of said memory cell on side walls of said first conductive pattern;
• removing said insulating film over said first conductive pattern;
• forming sidewall spacers, each comprised of an insulating film, in self-alignment with side walls of said second gate electrode;
• and
• forming a silicide layer for each of said first conductive pattern and said second gate electrode in self-alignment with respect to said sidewall spacers.

A semiconductor integrated circuit device comprising:

• a memory cell,
• wherein said memory cell includes a source region, a drain region, and a channel region interposed between said source region and said drain region, which are provided within a semiconductor region, and includes a first gate electrode, a second gate electrode, and an insulating film for electrically isolating said first gate electrode from said second gate electrode, which are provided over said channel region,
• wherein said channel region comprises a first channel region and a second channel region,
• wherein a first gate insulating film is provided between said first channel region and said first gate electrode,
• wherein a second gate insulating film is provided between said second channel region and said second gate electrode,
• wherein said second gate electrode is formed higher than said first gate electrode, and
• wherein said first gate electrode is formed in self-alignment with respect to sidewall spacers, each comprised of an insulating film, formed in self-alignment with respective side walls of said second gate electrode.

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

• forming a first conductive film over a memory cell forming region of a semiconductor substrate and forming an insulating film on said first conductive film;
• etching said insulating film and said first conductive film to form a first conductive pattern which serves as a first gate electrode of a memory cell;
• forming a second gate electrode of said memory cell on side walls of said first conductive pattern;
• removing said insulating film over said first conductive pattern;
• forming sidewall spacers, each comprised of an insulating film, in self-alignment with side walls of said second gate electrode;
• and
• etching said first conductive pattern in self-alignment with respect to said sidewall spacers to form corresponding first gate electrode.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate and includes, over said channel region, a first gate electrode disposed near said corresponding memory electrode with an insulating film interposed between said first gate electrode and said channel region, and a second gate electrode disposed on said channel region with an insulating film and a charge storage region interposed between said second gate electrode and said channel region and electrically isolated from said first gate electrode, and
• wherein said access circuit is capable of selecting a first state in which a first negative voltage is applied to said first well region to thereby form a reverse voltage applied state between said second gate electrode and said memory electrode near said second gate electrode and form an electric field for directing a first polarity charge from said well region side to said charge storage region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate and includes, over the channel region, a first gate electrode disposed near said one memory electrode with an insulating film interposed between said channel region and said first gate electrode, and a second gate electrode disposed near the other memory electrode on said channel region with an insulating film and a charge storage region interposed between said second gate electrode and said channel region and electrically isolated from said first gate electrode, and
• wherein said access circuit is capable of selecting a first state in which a first negative voltage is applied to said first well region to thereby apply a reverse voltage between said memory electrode near said second gate electrode and said first well region and apply to said second gate electrode a voltage for forming an electric field for directing a first polarity charge from said well region side to said charge storage region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate and includes, over said channel region, a first gate electrode disposed near a region for said one memory electrode with an insulating film interposed between said first gate electrode and said channel region, and a second gate electrode disposed near a region for the other memory electrode on said channel region with an insulating film and a charge storage region interposed between said second gate electrode and said channel region and electrically isolated from said first gate electrode, and
• wherein said access circuit is capable of selecting a first operation in which a negative voltage for forming a state of a reverse bias greater than or equal to a junction withstand voltage between said second gate electrode and said memory electrode near said second gate electrode is applied to said first well region to thereby inject a first polarity charge into said charge storage region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor;
• a first MIS transistor relatively thin in gate insulating film;
• and
• a second MIS transistor relatively thick in gate insulating film, said memory cell transistor, said first MIS transistor and said second MIS transistor being provided on a semiconductor substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate and includes, over said channel region, a first gate electrode disposed near a region for said one memory electrode with an insulating film interposed between said first gate electrode and said channel region, and a second gate electrode disposed near a region for the other memory electrode on said channel region with an insulating film and a charge storage region interposed between said second gate electrode and said channel region and electrically isolated from said first gate electrode, and is capable of storing information different according to a difference between amounts of a first polarity charge and a second polarity charge injected into said charge storage region,
• wherein said insulating film placed below said first gate electrode is substantially equal to said gate insulating film of said first MIS transistor in thickness, and
• wherein said well region is supplied with a negative voltage for forming a reverse bias state between said second gate electrode and said memory electrode near said second gate electrode when said first polarity charge is injected into said charge storage region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate and includes, over said channel region, memory gate electrodes separately disposed near the respective memory electrodes through insulating films and charge storage regions, and a control gate electrode disposed between both said memory gate electrodes with insulating films interposed therebetween and electrically isolated from said memory gate electrodes, and
• wherein said access circuit is capable of selecting a first state in which a negative voltage is applied to said first well region to thereby form a reverse bias state between said first well region and said one memory electrode and form an electric field for directing a first polarity charge from said well region side to the charge storage region on said corresponding one memory electrode side, and a third state in which a current is allowed to mutually flow from said one memory electrode to the other memory electrode through said channel region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access circuit for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate and includes, over said channel region, memory gate electrodes separately disposed near said respective memory electrodes through insulating films and charge storage regions, and a control gate electrode disposed between both said memory gate electrodes with insulating films interposed therebetween and electrically isolated from said memory gate electrodes, and
• wherein said access circuit is capable of selecting a first operation in which a negative voltage is applied to said first well region to thereby form a reverse bias state between said first well region and said one memory electrode and inject a first polarity charge into said one charge storage region, and a third operation in which a current is allowed to mutually flow from said one memory electrode to the other memory electrode through said channel region.

A semiconductor integrated circuit device comprising:

• a memory cell transistor provided on a semiconductor substrate;
• and
• an access memory for said memory cell provided on said substrate,
• wherein said memory cell transistor includes a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between said pair of memory electrodes, said pair of memory electrodes and said channel region being provided in a first well region of said semiconductor substrate and includes, over said channel region, a first gate electrode disposed near said corresponding memory electrode with a first gate insulating film interposed therebetween, and a second gate electrode disposed through a second gate insulating film and a charge storage region and electrically isolated from said first gate electrode, and
• wherein said first gate electrode is different in conductivity type from said second gate electrode.