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AssigneeKilopass Technologies, Inc.
InventorJack Zezhong Peng
Estimating the term…
A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.
A programmable read only memory cell useful in a memory array comprising:
A programmable read only memory cell useful in a memory array having row select lines, column select lines, and row program lines, the memory cell comprising a select transistor coupled in series with a two terminal data storage element, the data storage element comprising a doped region, an ultra-thin dielectric, and a conductive layer, the doped region connected to a row program line, the conductive layer connected to the source of said select transistor, the select transistor further having a gate coupled to a row select line and its drain connected to a column select line, the select transistor having a gate dielectric that has the same thickness as said ultra-thin dielectric.
A method of operating a programmable read only memory array comprising a plurality of row select lines, a plurality of column select lines, at least one row program line, and a plurality of memory cells at respective crosspoints of the row select lines and column select lines, each of the memory cells comprising a MOS field effect transistor coupled in series with a MOS data storage element between one of the column select lines and one of the at least one row program line, the MOS transistor further having a gate coupled to one of the row select lines and the MOS data storage element comprising an ultra-thin dielectric for physical storage of data, the method comprising:
A programmable read only memory array comprising a plurality of row select lines, a plurality of column select lines, at least one row program line, and a plurality of memory cells at respective crosspoints of the row select lines and column select lines in the memory, each of the memory cells comprising a select transistor coupled in series with a data storage element between one of the column select lines and said at least one program line, the select transistor further having a gate coupled to one of the row select lines and the data storage element comprising an ultra-thin dielectric for physical storage of data.
Dependencies are inferred from the claim text.
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Gate programmed, e.g. different gate material or no gate: gate dielectric programmed, e.g. different thickness
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: read-only digital stores…
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…
Read-only memory [rom] devices
Term end not estimated
The present invention relates to a nonvolatile programmable semiconductor memory, and more particularly to a nonvolatile programmable semiconductor memory cell that uses a breakdown phenomena in an ultra-thin dielectric such as a MOS gate dielectric to store digital information, and a memory array incorporating such cells.
Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. One commonly available type of nonvolatile memory is the programmable read-only memory (“PROM”), which uses word line—bit line crosspoint elements such as fuses, anti-fuses, and trapped charge devices such as the floating gate avalanche injection metal oxide semiconductor (“FAMOS”) transistor to store logical information. PROM typically is not reprogrammable.
An example of one type of PROM cell that uses the breakdown of a silicon dioxide layer in a capacitor to store digital data is disclosed in U.S. Pat. No. 6,215,140, issued Apr. 10, 2001 to Reisinger et al. The basic PROM disclosed by Reisinger et al. uses a series combination of an oxide capacitor and a junction diode as the crosspoint element. An intact capacitor represents the logic value 0, and an electrically broken-down capacitor represents the logic value 1. The thickness of the silicon dioxide layer is adjusted to obtain the desired operation specifications. Silicon dioxide has a breakdown charge of about 10 C/cm2 (Coulomb/cm2). If a voltage of 10 volts is applied to a capacitor dielectric with a thickness of 10 nm (resultant field strength 10 mV/cm), a current of about 1 mA/cm2 flows. With 10 volts, this thus results in a substantial amount of time for programming a memory cell. However, it is more advantageous to design the capacitor dielectric to be thinner, in order to reduce the high power loss which occurs during electrical breakdown. For example, a memory cell configuration having a capacitor dielectric with a thickness of 3 to 4 nm can be operated at about 1.5 V. The capacitor dielectric does not yet break down at this voltage, so that 1.5 V is sufficient to read data from the memory cell. Data are stored, for example, at 5 V, in which case one cell strand in a memory cell configuration can be programmed within about 1 ms. The energy loss which occurs in this case per cm2 of capacitor dielectric is then about 50 Watts (10 Coulomb*5 V). If the desired power loss is about 0.5 W, about 100 s are required to program a 1 Gigabit memory. If the permissible power losses are higher, the programming can be carried out correspondingly more quickly.
FIG. 1 is a schematic circuit diagram of a portion of a memory array in accordance with the present invention.
FIG. 2 is a partial layout diagram of a portion of the memory array represented by FIG. 1.
FIG. 3 is a cross-section diagram of an integrated circuit structure for the portion of the memory array corresponding to FIG. 2.
A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is, for example, high quality gate oxide of about 50 Å thickness or less, as is commonly available from presently available advanced CMOS logic processes, for example. Such oxides are commonly formed by deposition, by oxide growth from a silicon active region, or by some combination thereof. Other suitable dielectrics include oxide-nitride-oxide composites, compound oxides, and so forth.
In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.