Nonvolatile semiconductor memory

#The present invention relates to a semiconductor memory including a nonvolatile memory section and a buffer section thereof and particularly to a technique to realize high speed access with interleave operation by utilizing the nonvolatile memory section and the buffer section, for example, the technique which may be utilized effectively to a flash memory.

#The Japanese Patent Application Publication No. Hei 11(1999)-85609 describes a flash memory including a nonvolatile memory section and a buffer section thereof. According to this flash memory, the memory section can read or write data only in the unit of 8-bit or 16-bit and the buffer section provided is tacitly used to execute commands of erase, write and read operations for the flash memory because it is required to perform exchange of data in unit of single sector or a plurality of sectors such as 512 bytes in a host device.

#Moreover, the Japanese Patent Application Publication Nos. 2001-28428 (U.S. Pat. No. 6,438,028) and 2000-197876 (US Publication No. US-2002-0114192-A1) describe a flash memory utilizing an assist gate (AG) for separation of elements thereof. When the assist gate (AG) is used for separation of elements in the flash memory, a source and a drain can be used in common. In this case, since the source and drain locations are replaced with each other as required for the write and read operations, it is required to set the memory cells in every other cell as the operation object for many cells provided in parallel using in common the word line thereof. In short, since the adjacent memory cells use in common the source line and bit line connected to the source and drain, an operation error is generated when the adjacent memory cells are operated in parallel. Accordingly, the write and read operations to the flash memory described above using in common the word line have to be performed individually in the flash memories of the even numbers and that of the odd numbers.

#FIG. 1 illustrates a profile of 4-bank parallel interleave read operation of a flash memory as an embodiment of the present invention.

#FIG. 2 is a flowchart illustrating the control sequence of the interleave read operation of FIG. 1.

#FIG. 3 is a timing chart of the interleave read operation of FIG. 1.

#A structure of memory cell array in a flash memory as an example of the semiconductor memory of the present invention will be described first.

#FIG. 9 illustrates a cross-sectional structure of the flash memory. A nonvolatile memory cell MC is configured by forming a source electrode 108, a drain electrode 109 and a channel region on a semiconductor region (well region) 100, forming an assist MOS transistor section Qa in the side of the source electrode 108, while a memory MOS transistor section Qm in the side of the drain electrode 109. The assist MOS transistor section Qa includes an assist gate 106 on the channel region via a gate oxide film 104. The memory MOS transistor section Qm includes a floating gate 107 and a memory gate electrode 103 as the control gate on the channel region via a gate oxide film 102.

#FIG. 10 illustrates an example of a flash memory array (also referred to as only a memory cell array). Typical nonvolatile memory cells MC11 to MC14, MCn1 to MCn4 are allocated in a matrix, the memory gate electrodes 103 of the nonvolatile memory cells MC11 to MC14 allocated in the same raw are connected with a word line WL1, and the memory gate electrodes 103 of the nonvolatile memory cells MCn1 to MCn4 allocated in the same raw are connected with the word lines WLn. The nonvolatile memory cells MC11 to MC14 of the same raw are connected in series between the adjacent memory cells via the source electrode 108 and drain electrode 109. In the same manner, the nonvolatile memory cells MCn1 to MCn4 of the same raw are connected in series between the adjacent memory cells via the source electrode 108 and rain electrode 109 and these serially connected nodes are connected in the unit of column with the data lines DL1, DL2, DL3, DL4 and DL5.