Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics

A semiconductor memory device comprising:

• 2n word lines;
• a plurality of bit lines;
• a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;
• a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines;
• a sense amplifier for reading data out of said memory cells;
• a first means for simultaneously selecting a block of 2m (n>m) word lines among said 2n word lines;
• and
• a second means for not selecting a block of 2k (m>k) word lines among said 2m word lines, data being written to any memory cell transistor, which is contained in said 2k word lines and whose threshold voltage is lower than the potential of an unselected word line, so that the threshold voltage of said memory cell transistor exceeds the potential of said unselected word line, and a block of 2k word lines prepared outside said 2n word lines being used as redundant word lines.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;
• a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines;
• and
• a sense amplifier for reading data out of said memory cells, wherein each word line is controlled such that a drain current of a memory cell transistor connected to said word line is lower than a channel current thereof, when writing data to said cell transistor to increase the threshold voltage of said memory cell transistor to be higher than the potential of an unselected word line.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;
• a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines;
• and
• a sense amplifier for reading data out of said memory cells, wherein an output current of said sense amplifier is changed according to a combination of ON states of two load transistors having different capacities, to realize a normal data read operation, an erase verify operation, and a write verify operation.

A semiconductor memory device comprising:

• a plurality of real memory cells divided into blocks;
• a plurality of redundant memory cells to be replaced with defective ones of said real memory cells;
• a plurality of defective address specifying means for specifying defective addresses of the respective blocks of said real memory cells;
• and
• an address comparing means shared by said defective address specifying means, for comparing said defective addresses with addresses in said blocks of said real memory cells.

A semiconductor memory device comprising:

• a real cell array having a plurality of memory cells, and a plurality of redundant cells to be replaced with defective memory cells of said real cell array;
• a redundant information storing cell array for writing data to a defective address according to an externally provided address;
• a cell selection circuit for selecting said redundant information storing cell array according to the externally provided address;
• and
• a read circuit for reading an output of said redundant information storing cell array selected by said cell selection circuit, and providing a redundancy signal.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;
• and
• a write voltage supply transistor for supplying a write voltage to a drain of said memory cell, wherein said write voltage supply transistor is formed of a p-channel type MIS transistor, which effectively applies the write voltage to the drain of said memory cell.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;
• and
• a write voltage supply transistor for supplying a write voltage to a drain of said memory cell, wherein said write voltage supply transistor is formed of an n-channel type MIS transistor, and said semiconductor memory device comprises a step-up means being disposed to increase a gate voltage of said write voltage supply transistor at least up to a sum of the write voltage and a threshold voltage of said write voltage supply transistor.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, a threshold voltage of said MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of said MIS transistors being simultaneously discharged to collectively erase said memory cells;
• a first power source for applying a normal selection voltage to a selected word line to select memory cells connected to said word line, when reading data;
• and
• a second power source for establishing an unselected state on unselected word lines including memory cells that have been overerased by said collective erasing, when reading data.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, a threshold voltage of said MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of said MIS transistors being simultaneously discharged to collectively erase said memory cells;
• a first row decoder for applying a normal voltage to a selected word line to select memory cells connected to said word line, when reading data;
• and
• a second row decoder for applying a predetermined source voltage to the source of each memory cell connected to said selected word line, and applying an unselected state establishing voltage to the sources of memory cells, including those overerased by said collective erasing, connected to unselected word lines, when reading data.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof;
• a write-before-erase means for writing all memory cells of said memory cell array before erasing them;
• an erase means for erasing all of said written memory cells by said write-before-erase means and for verifying said erasing;
• an overerased cell detecting means for detecting overerased memory cells among said erased and verified memory cells by said erase means;
• and
• an overerased cell saving means for writing said overerased memory cells detected by said overerased cell detecting means, thereby saving said overerased memory cells.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• and
• a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable, wherein said nonvolatile memory cells are divided into a plurality of cell blocks to be selected according to a block selection signal provided by a block address buffer, each of said cell blocks has a data erasing means and a latching means for latching said block selection signal, and thereby data of said cell blocks that have latched said block selection signal are simultaneously erased.

A semiconductor memory device comprising:

• a first terminal for receiving a normal voltage;
• a second terminal for receiving a high voltage from a high-voltage supply means, and said high voltage being required to write or erase data and higher than said normal voltage required to read data;
• and
• a third terminal for providing said high-voltage supply means with a control signal that controls the supply of said high voltage.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells disposed at each intersection of said word lines and said bit lines, and a decoder circuit for selecting said memory cell according to an address signal in a normal decoding function and for carrying out a full selection operation or a nonselection operation of said word lines or said bit lines in a test function;
• and
• an output row or a decoding row connected to a first power source and a second power source, said first power source and a second power voltage, and said second power source supplying a reference voltage or said high voltage in response to a control signal.

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells disposed at each intersection of said word lines and said bit lines;
• a decoder circuit for selecting said memory cell according to an address signal in a normal decoding function and for carrying out a full selection operation or a nonselection operation of said word lines or said bit lines in a test function;
• and
• an output row or a decoding row connected to a first power source and a second power source, said first power source supplying a reference voltage, and said second power source supplying a reference voltage or said high voltage in response to a control signal.