Thin film magnetic memory device reducing a charging time of a data line in a data read operation

A thin film magnetic memory device comprising:

• a plurality of memory cells each having one of first and second electric resistances corresponding to magnetically written storage data;
• a reference cell having an electric resistance intermediate between said first and second electric resistances;
• a first data line being electrically coupled between first and second voltages via the selected memory cell corresponding to a selected address among said plurality of memory cells during data reading;
• a second data line being electrically coupled between said first and second voltages via said reference cell during said data reading;
• a level control circuit provided corresponding to said first and second data lines for changing levels of said first and second data lines to predetermined levels during said data reading;
• and
• a data read circuit for performing a data read operation in accordance with a difference between passing currents of said first and second data lines.

A thin film magnetic memory device comprising:

• a plurality of memory cells arranged in rows and columns, and each having one of first and second electric resistances corresponding to magnetically written storage data;
• a reference cell having an electric resistance intermediate between said first and second electric resistances;
• a first data line being electrically coupled between first and second voltages via the selected memory cell corresponding to a selected address among said plurality of memory cells during data reading;
• a second data line being electrically coupled between said first and second voltages via said reference cell during said data reading;
• a data read circuit for performing data read operation in accordance with a difference between passing currents of said first and second data lines,
• each of said first and second data lines including bit line portions arranged corresponding to the memory cell columns, respectively, and a local data line portion arranged corresponding to said data read circuit;
• a gate circuit for controlling connection between said bit line portion and said local data line portion in accordance with a column select instruction;
• and
• a precharge circuit provided corresponding to each of said memory cell columns for precharging said first and second bit lines before said data reading, and being deactivated in response to said column select instruction during said data reading.