Memory IC

A memory IC characterized in comprising:

• word lines;
• bit lines that traverse the word lines;
• first memory cell and second memory cell provided at intersections between the word lines and the bit lines;
• and
• an operation circuit that writes and reads data at the plurality of first memory cell and second memory cell, wherein
• first memory cell is composed of first capacitor and an N-type MOS transistor,
• second memory cell is composed of second capacitor and a P-type MOS transistor,
• a gate of the N-type MOS transistor and a gate the P-type MOS transistor are commonly connected to each identical one of the word lines, and either sources of the N-type MOS transistor and the P-type MOS transistor thereof or drains of the N-type MOS transistor and the P-type MOS transistor thereof are commonly connected to each identical one of the bit lines,
• electrodes on one side of the first and second capacitors are commonly connected to a plate electrode of the memory IC, and electrodes on the other side of first capacitor is connected to the sources or the drains of the N-type MOS transistor the N-type MOS transistor,
• on the other side of second capacitor is connected to the sources or the drains of the P-type MOS transistor and
• the operation circuit is composed of a circuit structure that freely writes and reads data in and from either one or both of first memory cell and second memory cell.