US 2003/0198078 A1 · Sensing method and apparatus for resistance memory device

Abstract

An MRAM memory integrated circuit is disclosed. Resistance, and hence logic state, is determined by discharging a first charged capacitor through an unknown cell resistive element to be sensed at a fixed voltage, and a pair of reference capacitors. The rate at which the parallel combination of capacitors discharge is between the discharge rate associated with a binary ‘1’ and ‘0’ value, and thus offers a reference for comparison.

Drawings

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Drawings

Claims35

Dependent claims

A resistance memory device, comprising:

a memory array comprising a plurality of row lines, a plurality of column lines, and a plurality of resistive elements, each resistive element connected to a row line and a column line, said resistive elements having one of a first resistance value which represents a first logical state and a second resistance value which represents a second logical state;
a sensing circuit for sensing the resistance value of a selected resistance element, said sensing circuit comprising:
a first capacitor and at least one second capacitor;
a charging circuit for charging said capacitors to a predetermined voltage value;
a reference resistance element;
a first discharge circuit for discharging said first capacitor through said selected resistive element and a second discharge circuit for discharging said at least one second capacitors through said reference resistance element;
and
a comparison circuit for comparing a discharge characteristic of said first capacitor with a discharge characteristic of said at least one second capacitor.

5 more elements

An MRAM memory device, comprising:

a memory array comprising a plurality of row lines, a plurality of column lines, and a plurality of resistive elements, each resistive element connected to a row line and a column line, said resistive elements having one of a first resistance value which represents a first logical state and a second resistance value which represents a second logical state;
a sensing circuit for sensing the resistance value of a selected resistance element, said sensing circuit comprising:
a first capacitor and at least one second capacitor;
a charging circuit for charging said capacitors to a predetermined voltage value;
a reference resistance element;
a first discharge circuit for discharging said first capacitor through said selected resistive element and a second discharge circuit for discharging said at least one second capacitors through said reference resistance element;
and
a comparison circuit for comparing a discharge characteristic of said first capacitor with a discharge characteristic of said at least one second capacitor.

5 more elements

An processor circuit, comprising:

a CPU;
an resistive memory circuit, further comprising:
a memory array comprising a plurality of row lines, a plurality of column lines, and a plurality of resistive elements, each resistive element connected to a row line and a column line, said resistive elements having one of a first resistance value which represents a first logical state and a second resistance value which represents a second logical state;
a sensing circuit for sensing the resistance value of a selected resistance element, said sensing circuit comprising:
a first capacitor and at least one second capacitor;
a charging circuit for charging said capacitors to a predetermined voltage value;
a reference resistance element;
a first discharge circuit for discharging said first capacitor through said selected resistive element and a second discharge circuit for discharging said at least one second capacitors through said reference resistance element;
and
a comparison circuit for comparing a discharge characteristic of said first capacitor with a discharge characteristic of said at least one second capacitor.

7 more elements

An processor circuit, comprising:

a CPU;
an MRAM memory circuit, further comprising:
a memory array comprising a plurality of row lines, a plurality of column lines, and a plurality of resistive elements, each resistive element connected to a row line and a column line, said resistive elements having one of a first resistance value which represents a first logical state and a second resistance value which represents a second logical state;
a sensing circuit for sensing the resistance value of a selected resistance element, said sensing circuit comprising:
a first capacitor and at least one second capacitor;
a charging circuit for charging said capacitors to a predetermined voltage value;
a reference resistance element;
a first discharge circuit for discharging said first capacitor through said selected resistive element and a second discharge circuit for discharging said at least one second capacitors through said reference resistance element;
and
a comparison circuit for comparing a discharge characteristic of said first capacitor with a discharge characteristic of said at least one second capacitor.

7 more elements

Dependencies are inferred from the claim text.

Description2,519 words

Summary366 words

#The present invention relates to the field of resistor-based memory circuits. More particularly, it relates to a method for precisely sensing the resistance value of a resistor-based memory cell, for example, a Magnetic Random Access Memory (MRAM) magnetic memory cell.

#A resistor-based memory such as a magnetic random access memory (MRAM) typically includes an array of resistor-based magnetic memory cells. The logic state of such a magnetic memory cell is indicated by its resistance. One resistance value, e.g., the higher value, may be used to signify a logic high while another resistance value, e.g., the lower value, may be used to signify a logic low. The value stored in each memory cell can be determined by measuring the resistance value of the cell to determine whether the cell corresponds to a logic high or low. Such direct measurements are often difficult to simply and easily implement and require a number of comparators which increases the cost and size of the memory circuit. A simplified, more reliable method of sensing the resistance value of a resistor-based memory cell is desired.

#The present invention provides a simple and reliable method and apparatus for sensing the logic state of a resistor-based memory cell. Resistance is measured by first charging a first capacitor to a predetermined voltage, discharging the first capacitor through a resistance to be measured while discharging a second capacitor through an associated reference resistance of known value and comparing the discharge characteristics e.g. the discharge voltage of two capacitors to determine a value of resistance to be measured relative to the reference resistance.

Brief description of the drawings7 figures

#The foregoing and other features and advantages of the invention will become more apparent from the detailed description of the exemplary embodiments of the invention given below with reference to the accompanying drawings in which:

#FIG. 1 shows the invention employed in an exemplary MRAM device;

#FIG. 2 shows a schematic diagram of one aspect of the invention;

Detailed description2,032 words

#A portion of a MRAM array 100 with which the present invention may be used is shown in FIG. 1. The logical state of an MRAM memory element e.g. 204 is represented by the resistance of that element. In the present invention, resistance is determined by holding a voltage constant across a cell's resistive element and comparing a voltage produced by the current that flows through that resistive element with a voltage produced by the current flow through a known reference resistance. To read the binary state of a memory cell element, the absolute magnitude of resistance need not be known; only whether the resistance is above or below a value that is intermediate to the logic high and logic low values. Accordingly, to provide a reference current flow for comparison purposes the resistive elements within rightmost column 108 of array 100 are preprogrammed to hold all ‘0’ values, while those within column 110 immediately to its left are preprogrammed to hold all ‘1’ values. The current flowing through these two columns when a particular row line of the array 100 is selected by grounding a rowline, e.g. rowline 120, will heretofore be designated as I0 and I1 as shown in FIG. 1.

#During the reading process, all column and row lines are driven with the same array voltage VA, except for the one row line, e.g. 120 that is desired to be read. That row line 120 is driven to ground. When row 120 is grounded, a resistive element of a selected column, e.g. column 109, can be read by a sensing circuit 300 described below As shown in FIG. 1, both ends of all resistive elements not being measured are maintained at the same potential, VA. Thus, unwanted current flow through these resistive elements due to “sneak” resistance is negligible. A current Isense flows through the grounded resistive element of a selected column within the row 120 for allowing measurement of the resistance by the sensing circuit 300 (not shown in FIG. 1).

#FIG. 2 shows a circuit 200 for regulating current through and voltage across a resistive element 204 being measured. An operational amplifier 220 has one terminal 222 connected to VA, while the other terminal 224 is connected to the column line 109 for the resistance element 204 which is being sensed. The gate 242 of NMOS transistor 240 is connected to the output of operational amplifier 220. The source 246 of transistor 240 is connected to one terminal of the resistive element 204 being read, while the other terminal of resistive element 204 is driven to ground by the grounding of wordline 120 described earlier. Operational amplifier 220 and transistor 240 act in concert to keep one terminal of resistive element 204 stably at VA despite the fact that the other terminal is grounded. In this way, Isense can flow through transistor 240 and resistive element 204, while current lost through sneak resistor 225 is minimized.

Facts

Application

10/422,849Filed 25 Apr 2003

Priority

28 Aug 2001

Published

23 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification3 codes

G11C 11/14
Using magnetic elements: using thin-film elements
G11C 7/062
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of non-latching type, e.g. comparators,…
G11C
Static stores

Family

Application09/939,655Continuation · filed 28 Aug 2001

Application10/422,849Continuation · filed 25 Apr 2003

US 2003/0043616 A1Published application

US 6,577,525 B2Related patent

US 6,741,490 B2Related patent

US 2003/0198078 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

28 Aug 2001Priority claimedParent application 09/939,655
25 Apr 2003Application filedUS 10/422,849
23 Oct 2003PublishedUS 2003/0043616 A1
12 May 2016Assigned to U.S. Bank National Association, AS Collateral Agentsecurity interest
2 Jun 2016Assigned to Morgan Stanley Senior Funding, Inc., AS Collateral Agentpatent security agreement
8 Jun 2017Assigned to U.S. Bank National Association, AS Collateral Agentcorrective assignment to correct the replace erroneously filed patent #7358718 with the correct patent #7358178 previously recorded on reel 038669 frame 0001. assignor(s) hereby confirms the security interest.
13 Jul 2018Assigned to Jpmorgan Chase Bank, N.A., AS Collateral Agentsecurity interest
23 Aug 2018Assigned to Micron Technology, Inc.release of security interest
9 Oct 2019Assigned to Micron Technology, Inc.release of security interest
12 Nov 2019Assigned to Micron Technology, Inc., Micron Semiconductor Products, Inc.release of security interest

Sensing method and apparatus for resistance memory device

Life of this patent

Sensing method and apparatus for resistance memory device

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims35

Description2,519 words

Drawings

Classification3 codes

Life of this patent

Description2,519 words