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AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsMichihito Ueda, Takashi Ohtsuka, Kiyoyuki Morita
Estimating the term…
A semiconductor device includes: a control-voltage supply unit 110; an MOS transistor including a gate electrode 109 and drain and source regions 103a and 103b; a dielectric capacitor 104; and a resistor 106. The dielectric capacitor 104 and the resistor 106 are disposed in parallel and interposed between the gate electrode 109 and the control-voltage supply unit 110. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor 104 and the gate electrode 109 upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.
A semiconductor device comprising:
A semiconductor device, comprising:
A method for driving a semiconductor device including a control-voltage supply unit, a field-effect transistor including a gate electrode having a function of accumulating a charge, a capacitor, and a resistor, the capacitor and the resistor being disposed in parallel and interposed between the control-voltage supply unit and the gate electrode,
Dependencies are inferred from the claim text.
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Term end not estimated
The present invention relates to semiconductor devices and methods for driving the same. More particularly, the present invention relates to semiconductor devices which are applicable to neural network computers (neurocomputers), for example, and allows multilevel information to be stored therein, and also relates to methods for driving the devices.
As multimedia has been developed, semiconductor devices are more and more required to improve their performance. For example, to process a large capacity of digital information, even CPUs of personal computers operating at high speeds of 1 GHz or more have come onto the market.
To meet such a demand for improving the performance of semiconductor devices, semiconductor fabricators have improved the performance mainly with techniques of downsizing the semiconductor devices.
FIG. 1 is a top plan view showing a multilevel memory according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of the multilevel memory of the first embodiment, taken along the line II-II in FIG. 1.
FIG. 3 is a cross-sectional view of the multilevel memory of the first embodiment, taken along the line III-III in FIG. 1.
Embodiment 1
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a top plan view of a multilevel memory according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 1. In FIGS. 1, 2 and 3, identical components are denoted by respectively identical reference numerals. In FIG. 1, only the components located on the uppermost surface are indicated by solid lines. Some of reference numerals of the portions that are commonly shown in FIGS. 2 and 3 are omitted for better viewability.