Bi-level digit line architecture for high density DRAMS

A method for differential noise reduction for an integrated circuit memory having a plurality of memory cells of a semiconductor device, comprising:

• fabricating a first digit line having a width and a second digit line having a width, the first digit line and the second digit line extending in a first conductive level and a second conductive level above a plane extending along a portion of a surface of the integrated circuit memory device such that the first digit line and second digit line are substantially vertically aligned within the widths thereof and vertically stacked one from the other in the plane;
• providing a vertical conductive twist to locate a portion of each of the first digit line and the second digit line in both the first conductive level and the second conductive level;
• coupling an equal number of the plurality of memory cells of the integrated circuit memory device to portions of the first digit line and the second digit line located in a lower conductive level of the first conductive level and the second conductive level;
• electrically balancing the first digit line and the second digit line when vertically stacked one atop the other;
• and
• isolating a plurality of pairs of adjacent memory cells of the plurality using an isolation region.

A noise reduction method for a memory device having a plurality of memory cells of a semiconductor device, comprising:

• fabricating a first digit line having a width and a second digit line having a width, the first digit line and the second digit line extending in a first conductive level and a second conductive level above a plane extending along a portion of a surface of the memory device such that the first digit line and second digit line are substantially vertically aligned within the widths thereof and vertically stacked one from the other in the plane;
• providing a vertical conductive twist to locate a portion of each of the first digit line and the second digit line in both the first conductive level and the second conductive level;
• coupling an equal number of the plurality of memory cells of the memory device to portions of the first digit line and the second digit line located in a lower conductive level of the first conductive level and the second conductive level;
• electrically balancing the first digit line and the second digit line when vertically stacked one atop the other;
• and
• isolating a plurality of adjacent memory cells of the plurality using an isolation region.