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AssigneeInternational Business Machines Corporation
InventorsFred J. Towler, Reid A. Wistort, Jason Rotella
Estimating the term…
A method for determining a desired operating impedance for a computer memory circuit is disclosed, the computer memory circuit having a plurality of discrete, selectively adjustable impedance values associated therewith. In an exemplary embodiment of the invention, the method includes applying, to a reference circuit, a test impedance value to a reference circuit. The test impedance value is controlled by a binary count. A determination is made, based upon the applied test impedance value, whether the reference circuit is in either a first state or a second state. The binary count is incremented if the reference circuit is in the first state and decremented if the reference circuit is in the second state. A condition is determined in which the reference circuit oscillates between the first state and said second state, and a pair of binary count values is stored. The desired operating impedance for the computer memory circuit corresponds to the lower of the stored pair of binary count values.
A method for determining a desired operating impedance for an operating circuit, the operating circuit having a plurality of discrete, selectively adjustable impedance values associated therewith, the method comprising:
A method for determining a desired operating impedance for a computer memory circuit, the computer memory circuit having a plurality of discrete, selectively adjustable impedance values associated therewith, the method comprising:
An apparatus for automatically adjusting the margin of an operating impedance for an operating circuit, the operating circuit having a plurality of discrete, selectively adjustable impedance values associated therewith, the apparatus comprising:
An apparatus for automatically adjusting the pull-up margin of a match line circuit in a content addressable memory (CAM), the apparatus comprising:
A match line circuit for use in a content addressable memory (CAM) device, comprising:
Dependencies are inferred from the claim text.
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Marginal testing, e.g. race, voltage or current testing: of impedance
Digital stores in which information comprising one or more characteristic parts is
Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out…
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters
Term end not estimated
The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for automatically adjusting the pull-up margin of a match line circuit used in conjunction with a content addressable memory (CAM).
A content addressable memory (CAM) is a storage device in which storage locations are identified by their contents, not by names or positions. A search argument is presented to the CAM and the location that matches the argument asserts a corresponding match line. One use for such a memory is in dynamically translating logical addresses to physical addresses in a virtual memory system. In this case, the logical address is the search argument and the physical address is produced as a result of the dynamic match line selecting the physical address from a storage location in a random access memory (RAM). CAMs are also frequently used for Internet address searching.
A conventional CAM array 1 having n-bit words is shown in FIG. 1 to include a row of n CAM cells 10 coupled to an associated word line WL. Each CAM cell 10 includes a latch, formed by CMOS inverters 12 and 14, for storing a bit of data. Opposite sides of the latch are coupled to associated complementary bit lines BL and BL bar via pass transistors 16 and 18, respectively, where each transistor has a gate coupled to the associated word line WL. The output terminal of the inverter I2 is coupled to the gate of an NMOS pass transistor 20, and the output terminal of the inverter I4 is coupled to the gate of an NMOS transistor 22. Transistor 20 is coupled between the associated bit line BL and the gate of an NMOS pull-down transistor 24, and transistor 22 is coupled between the associated complementary bit line BL bar and the gate of pull-down transistor 24. Pull-down transistor 24 is coupled between ground potential and a match line ML associated with the CAM word formed by the cells 10. A PMOS pull-up transistor 26 is coupled between a supply voltage VDD and the match line ML.
Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
FIG. 1 is a schematic diagram of a CAM cell array configured to an existing match line circuit having a single pull-up device;
FIG. 2 is a schematic diagram of a low-power match line circuit which may be implemented as an alternative to the circuit of FIG. 1;
Referring initially to FIG. 2, there is shown a schematic diagram of one possible embodiment of a low-power, match line circuit 200 for a CAM sense amplifier. Match line circuit 200 replaces pull-up PFET 26 and buffer 28 of FIG. 1. For ease of description, only one CAM cell is depicted in FIG. 2. Match line circuit 200 includes pull-up PFET T4 coupled to a voltage supply VDD and a pull-down NFET T6 connected to ground. The gates of both T4 and T6 are coupled to an ENABLE signal which is initially biased at logic high (e.g., at VDD potential) and which goes to logic low (e.g., at ground potential) during a search or compare operation. In addition, the drains of T4 and T6 are coupled to match line ML and thereby define a node labeled MATCH in FIG. 2.
The ENABLE signal is also coupled to an inverter I1 which, in turn, has an output thereof connected to the gate of pull-up PFET T5. Another pull-down NFET T8 has its drain connected to the drain of T5, thereby defining a node labeled FLOAT, which is described in further detail hereinafter. The gate of T8 is further connected to the MATCH node. Finally, a second inverter I2 has an input connected to the FLOAT node and an output which defines a node labeled HIT.
The operation of the match line circuit 200 is understood with reference to the following description. In between search (compare) operations, ENABLE is biased at logic high, as stated earlier. Thus, NFET T6 is rendered conductive, pulling MATCH to ground. As a result, SL and SL bar may remain in their previous state, thereby eliminating the power required to precharge them. Further, the conductive state of T6 prevents any DC current flowing during a standby mode. This is in contrast to the circuitry shown in FIG. 1, wherein the match line is biased to VDD prior to a data comparison operation, and BLIBL bar must be switched to ground in order to eliminate a DC path.