Dense content addressable memory cell

#This invention relates to memory cells and more particularly relates to content addressable memory cells.

#Many memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory access. The time required to find an item stored in memory can be reduced considerably if the stored data item can be identified for access by the content of the data itself rather than by its address. Memory that is accessed in this way is called content-addressable memory (CAM). CAM provides a performance advantage over other memory search algorithms (such as binary and tree-based searches or look-aside tag buffers) by comparing the desired information against the stored data simultaneously, often resulting in an order-of-magnitude reduction of search time.

#A CAM cell is the basic circuit determining the speed, size and power consumption of a CAM system. Known CAM cells require a substantial number of transistors that consume power and require a substantial amount of area on a chip. In addition, match circuitry employed in known CAM cells requires a substantial amount of time for proper operation. This invention addresses these problems and provides a solution.

#FIG. 1 is a schematic diagram of one embodiment of the invention.

#Referring to FIG. 1, one embodiment of a CAM cell 10 embodying the invention includes a word line 12 and bit lines 14 and 16. Cell 10 includes a semi-static (SSRAM) or dynamic random access memory type circuit 20 including a source 24 of a reference voltage, such as ground potential. Circuit 20 also includes p-channel transistors 26-27 and n-channel transistors 30-31 cross-coupled as shown. Transistors 26-27 serve as both reading and writing transistors also called access and loading transistors. Transistors 26-27 may comprise low voltage threshold transistors in order to compensate for the leakage in circuit 20. To make sure that the leakage through the p-channel transistors compensates for the leakage through the n-channel transistors, the voltage on word line 12 can be adaptively changed for proper operation at all process corners and temperatures. If necessary, line 12 is reduced in voltage below VDD (the supply voltage) so that transistors 26 and 27 are partially conductive, thus allowing current conduction that compensates for leakage by transistors 30 and 31. In addition, p-channel transistors 26-27 are better than n-channel transistors to supply charges at circuit points 35 and 36 to maintain the stored data. Bit lines are kept at VDD (precharged) in a default or a no activity state to provide the charges.

#Thus, the embodiment shown in FIG. 1 is able to store complementary bits of data with only four transistors, while conventional SRAM cells require six transistors. By using the embodiment shown in FIG. 1, substantial area is saved on a chip incorporating the cell shown in FIG. 1.

#Voltage levels corresponding to stored data bits are stored at points 35-36 of circuit 20. The data bits stored at points 35-36 are complements of each other.